Lines Matching refs:hw
43 * @hw: pointer to the hardware structure
47 static void i40e_adminq_init_regs(struct i40e_hw *hw)
50 if (i40e_is_vf(hw)) {
51 hw->aq.asq.tail = I40E_VF_ATQT1;
52 hw->aq.asq.head = I40E_VF_ATQH1;
53 hw->aq.asq.len = I40E_VF_ATQLEN1;
54 hw->aq.asq.bal = I40E_VF_ATQBAL1;
55 hw->aq.asq.bah = I40E_VF_ATQBAH1;
56 hw->aq.arq.tail = I40E_VF_ARQT1;
57 hw->aq.arq.head = I40E_VF_ARQH1;
58 hw->aq.arq.len = I40E_VF_ARQLEN1;
59 hw->aq.arq.bal = I40E_VF_ARQBAL1;
60 hw->aq.arq.bah = I40E_VF_ARQBAH1;
62 hw->aq.asq.tail = I40E_PF_ATQT;
63 hw->aq.asq.head = I40E_PF_ATQH;
64 hw->aq.asq.len = I40E_PF_ATQLEN;
65 hw->aq.asq.bal = I40E_PF_ATQBAL;
66 hw->aq.asq.bah = I40E_PF_ATQBAH;
67 hw->aq.arq.tail = I40E_PF_ARQT;
68 hw->aq.arq.head = I40E_PF_ARQH;
69 hw->aq.arq.len = I40E_PF_ARQLEN;
70 hw->aq.arq.bal = I40E_PF_ARQBAL;
71 hw->aq.arq.bah = I40E_PF_ARQBAH;
77 * @hw: pointer to the hardware structure
79 enum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
83 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
85 (hw->aq.num_asq_entries *
91 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
92 (hw->aq.num_asq_entries *
95 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
104 * @hw: pointer to the hardware structure
106 enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
110 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
112 (hw->aq.num_arq_entries *
121 * @hw: pointer to the hardware structure
126 void i40e_free_adminq_asq(struct i40e_hw *hw)
128 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
129 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
134 * @hw: pointer to the hardware structure
139 void i40e_free_adminq_arq(struct i40e_hw *hw)
141 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
146 * @hw: pointer to the hardware structure
148 static enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)
160 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
161 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
164 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
167 for (i = 0; i < hw->aq.num_arq_entries; i++) {
168 bi = &hw->aq.arq.r.arq_bi[i];
169 ret_code = i40e_allocate_dma_mem(hw, bi,
171 hw->aq.arq_buf_size,
177 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
180 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
205 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
206 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
213 * @hw: pointer to the hardware structure
215 static enum i40e_status_code i40e_alloc_asq_bufs(struct i40e_hw *hw)
222 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
223 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
226 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
229 for (i = 0; i < hw->aq.num_asq_entries; i++) {
230 bi = &hw->aq.asq.r.asq_bi[i];
231 ret_code = i40e_allocate_dma_mem(hw, bi,
233 hw->aq.asq_buf_size,
245 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
246 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
253 * @hw: pointer to the hardware structure
255 static void i40e_free_arq_bufs(struct i40e_hw *hw)
260 for (i = 0; i < hw->aq.num_arq_entries; i++)
261 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
264 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
267 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
272 * @hw: pointer to the hardware structure
274 static void i40e_free_asq_bufs(struct i40e_hw *hw)
279 for (i = 0; i < hw->aq.num_asq_entries; i++)
280 if (hw->aq.asq.r.asq_bi[i].pa)
281 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
284 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
287 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
290 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
295 * @hw: pointer to the hardware structure
299 static enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw)
305 wr32(hw, hw->aq.asq.head, 0);
306 wr32(hw, hw->aq.asq.tail, 0);
309 if (!i40e_is_vf(hw))
310 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
312 if (i40e_is_vf(hw))
313 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
315 wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
316 wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
319 reg = rd32(hw, hw->aq.asq.bal);
320 if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
328 * @hw: pointer to the hardware structure
332 static enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw)
338 wr32(hw, hw->aq.arq.head, 0);
339 wr32(hw, hw->aq.arq.tail, 0);
342 if (!i40e_is_vf(hw))
343 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
345 if (i40e_is_vf(hw))
346 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
348 wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
349 wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
352 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
355 reg = rd32(hw, hw->aq.arq.bal);
356 if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))
364 * @hw: pointer to the hardware structure
368 * in the hw->aq structure:
369 * - hw->aq.num_asq_entries
370 * - hw->aq.arq_buf_size
375 enum i40e_status_code i40e_init_asq(struct i40e_hw *hw)
379 if (hw->aq.asq.count > 0) {
386 if ((hw->aq.num_asq_entries == 0) ||
387 (hw->aq.asq_buf_size == 0)) {
392 hw->aq.asq.next_to_use = 0;
393 hw->aq.asq.next_to_clean = 0;
396 ret_code = i40e_alloc_adminq_asq_ring(hw);
401 ret_code = i40e_alloc_asq_bufs(hw);
406 ret_code = i40e_config_asq_regs(hw);
411 hw->aq.asq.count = hw->aq.num_asq_entries;
415 i40e_free_adminq_asq(hw);
419 i40e_free_asq_bufs(hw);
427 * @hw: pointer to the hardware structure
431 * in the hw->aq structure:
432 * - hw->aq.num_asq_entries
433 * - hw->aq.arq_buf_size
438 enum i40e_status_code i40e_init_arq(struct i40e_hw *hw)
442 if (hw->aq.arq.count > 0) {
449 if ((hw->aq.num_arq_entries == 0) ||
450 (hw->aq.arq_buf_size == 0)) {
455 hw->aq.arq.next_to_use = 0;
456 hw->aq.arq.next_to_clean = 0;
459 ret_code = i40e_alloc_adminq_arq_ring(hw);
464 ret_code = i40e_alloc_arq_bufs(hw);
469 ret_code = i40e_config_arq_regs(hw);
474 hw->aq.arq.count = hw->aq.num_arq_entries;
478 i40e_free_adminq_arq(hw);
486 * @hw: pointer to the hardware structure
490 enum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw)
494 i40e_acquire_spinlock(&hw->aq.asq_spinlock);
496 if (hw->aq.asq.count == 0) {
502 wr32(hw, hw->aq.asq.head, 0);
503 wr32(hw, hw->aq.asq.tail, 0);
504 wr32(hw, hw->aq.asq.len, 0);
505 wr32(hw, hw->aq.asq.bal, 0);
506 wr32(hw, hw->aq.asq.bah, 0);
508 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
511 i40e_free_asq_bufs(hw);
514 i40e_release_spinlock(&hw->aq.asq_spinlock);
520 * @hw: pointer to the hardware structure
524 enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw)
528 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
530 if (hw->aq.arq.count == 0) {
536 wr32(hw, hw->aq.arq.head, 0);
537 wr32(hw, hw->aq.arq.tail, 0);
538 wr32(hw, hw->aq.arq.len, 0);
539 wr32(hw, hw->aq.arq.bal, 0);
540 wr32(hw, hw->aq.arq.bah, 0);
542 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
545 i40e_free_arq_bufs(hw);
548 i40e_release_spinlock(&hw->aq.arq_spinlock);
554 * @hw: pointer to the hardware structure
556 static void i40e_resume_aq(struct i40e_hw *hw)
559 hw->aq.asq.next_to_use = 0;
560 hw->aq.asq.next_to_clean = 0;
562 i40e_config_asq_regs(hw);
564 hw->aq.arq.next_to_use = 0;
565 hw->aq.arq.next_to_clean = 0;
567 i40e_config_arq_regs(hw);
572 * @hw: pointer to the hardware structure
575 * in the hw->aq structure:
576 * - hw->aq.num_asq_entries
577 * - hw->aq.num_arq_entries
578 * - hw->aq.arq_buf_size
579 * - hw->aq.asq_buf_size
581 enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
583 struct i40e_adminq_info *aq = &hw->aq;
601 i40e_adminq_init_regs(hw);
604 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
607 ret_code = i40e_init_asq(hw);
612 ret_code = i40e_init_arq(hw);
617 if (i40e_is_vf(hw))
624 ret_code = i40e_aq_get_firmware_version(hw,
635 i40e_resume_aq(hw);
641 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
642 &hw->nvm.version);
643 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
644 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
645 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
646 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr);
647 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF),
649 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)),
651 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
656 switch (hw->mac.type) {
661 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;
662 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
664 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE;
671 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
681 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
686 hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT;
694 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
695 hw->nvm_release_on_done = FALSE;
696 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
704 i40e_shutdown_arq(hw);
706 i40e_shutdown_asq(hw);
717 * @hw: pointer to the hardware structure
719 enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)
723 if (i40e_check_asq_alive(hw))
724 i40e_aq_queue_shutdown(hw, TRUE);
726 i40e_shutdown_asq(hw);
727 i40e_shutdown_arq(hw);
728 i40e_destroy_spinlock(&hw->aq.asq_spinlock);
729 i40e_destroy_spinlock(&hw->aq.arq_spinlock);
731 if (hw->nvm_buff.va)
732 i40e_free_virt_mem(hw, &hw->nvm_buff);
739 * @hw: pointer to the hardware structure
743 u16 i40e_clean_asq(struct i40e_hw *hw)
745 struct i40e_adminq_ring *asq = &(hw->aq.asq);
753 while (rd32(hw, hw->aq.asq.head) != ntc) {
754 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,
755 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
762 cb_func(hw, &desc_cb);
780 * @hw: pointer to the hw struct
785 bool i40e_asq_done(struct i40e_hw *hw)
790 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
796 * @hw: pointer to the hw struct
805 enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
819 i40e_acquire_spinlock(&hw->aq.asq_spinlock);
821 hw->aq.asq_last_status = I40E_AQ_RC_OK;
823 if (hw->aq.asq.count == 0) {
824 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
830 val = rd32(hw, hw->aq.asq.head);
831 if (val >= hw->aq.num_asq_entries) {
832 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
838 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
865 if (buff_size > hw->aq.asq_buf_size) {
866 i40e_debug(hw,
875 i40e_debug(hw,
889 if (i40e_clean_asq(hw) == 0) {
890 i40e_debug(hw,
898 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
906 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
922 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n");
923 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
925 (hw->aq.asq.next_to_use)++;
926 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
927 hw->aq.asq.next_to_use = 0;
929 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
941 if (i40e_asq_done(hw))
945 } while (total_delay < hw->aq.asq_cmd_timeout);
949 if (i40e_asq_done(hw)) {
957 i40e_debug(hw,
972 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
975 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,
977 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
987 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
988 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
992 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
999 i40e_release_spinlock(&hw->aq.asq_spinlock);
1022 * @hw: pointer to the hw struct
1030 enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
1035 u16 ntc = hw->aq.arq.next_to_clean;
1047 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
1049 if (hw->aq.arq.count == 0) {
1050 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
1057 if (!i40e_is_vf(hw))
1058 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1060 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
1068 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
1071 hw->aq.arq_last_status =
1076 i40e_debug(hw,
1079 hw->aq.arq_last_status);
1088 hw->aq.arq.r.arq_bi[desc_idx].va,
1091 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n");
1092 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
1093 hw->aq.arq_buf_size);
1099 bi = &hw->aq.arq.r.arq_bi[ntc];
1103 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1110 wr32(hw, hw->aq.arq.tail, ntc);
1113 if (ntc == hw->aq.num_arq_entries)
1115 hw->aq.arq.next_to_clean = ntc;
1116 hw->aq.arq.next_to_use = ntu;
1118 i40e_nvmupd_check_wait_event(hw, LE16_TO_CPU(e->desc.opcode), &e->desc);
1122 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1124 i40e_release_spinlock(&hw->aq.arq_spinlock);