dev/ixl/i40e_adminq.c

51 		hw->aq.asq.tail = I40E_VF_ATQT1;
52 		hw->aq.asq.head = I40E_VF_ATQH1;
53 		hw->aq.asq.len  = I40E_VF_ATQLEN1;
54 		hw->aq.asq.bal  = I40E_VF_ATQBAL1;
55 		hw->aq.asq.bah  = I40E_VF_ATQBAH1;
62 		hw->aq.asq.tail = I40E_PF_ATQT;
63 		hw->aq.asq.head = I40E_PF_ATQH;
64 		hw->aq.asq.len  = I40E_PF_ATQLEN;
65 		hw->aq.asq.bal  = I40E_PF_ATQBAL;
66 		hw->aq.asq.bah  = I40E_PF_ATQBAH;
83 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
91 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
95 		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
128 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
129 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
222 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
226 	hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
230 		bi = &hw->aq.asq.r.asq_bi[i];
245 		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
246 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
280 		if (hw->aq.asq.r.asq_bi[i].pa)
281 			i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
284 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
287 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
290 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
305 	wr32(hw, hw->aq.asq.head, 0);
306 	wr32(hw, hw->aq.asq.tail, 0);
310 		wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
313 		wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
315 	wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
316 	wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
319 	reg = rd32(hw, hw->aq.asq.bal);
320 	if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
379 	if (hw->aq.asq.count > 0) {
392 	hw->aq.asq.next_to_use = 0;
393 	hw->aq.asq.next_to_clean = 0;
411 	hw->aq.asq.count = hw->aq.num_asq_entries;
496 	if (hw->aq.asq.count == 0) {
502 	wr32(hw, hw->aq.asq.head, 0);
503 	wr32(hw, hw->aq.asq.tail, 0);
504 	wr32(hw, hw->aq.asq.len, 0);
505 	wr32(hw, hw->aq.asq.bal, 0);
506 	wr32(hw, hw->aq.asq.bah, 0);
508 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */
559 	hw->aq.asq.next_to_use = 0;
560 	hw->aq.asq.next_to_clean = 0;
745 	struct i40e_adminq_ring *asq = &(hw->aq.asq);
747 	u16 ntc = asq->next_to_clean;
751 	desc = I40E_ADMINQ_DESC(*asq, ntc);
752 	details = I40E_ADMINQ_DETAILS(*asq, ntc);
753 	while (rd32(hw, hw->aq.asq.head) != ntc) {
755 			   "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
767 		if (ntc == asq->count)
769 		desc = I40E_ADMINQ_DESC(*asq, ntc);
770 		details = I40E_ADMINQ_DETAILS(*asq, ntc);
773 	asq->next_to_clean = ntc;
775 	return I40E_DESC_UNUSED(asq);
790 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
823 	if (hw->aq.asq.count == 0) {
830 	val = rd32(hw, hw->aq.asq.head);
838 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
898 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
906 		dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
925 	(hw->aq.asq.next_to_use)++;
926 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)
927 		hw->aq.asq.next_to_use = 0;
929 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
987 		if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {