dev/ixl/i40e_adminq.c

56 		hw->aq.arq.tail = I40E_VF_ARQT1;
57 		hw->aq.arq.head = I40E_VF_ARQH1;
58 		hw->aq.arq.len  = I40E_VF_ARQLEN1;
59 		hw->aq.arq.bal  = I40E_VF_ARQBAL1;
60 		hw->aq.arq.bah  = I40E_VF_ARQBAH1;
67 		hw->aq.arq.tail = I40E_PF_ARQT;
68 		hw->aq.arq.head = I40E_PF_ARQH;
69 		hw->aq.arq.len  = I40E_PF_ARQLEN;
70 		hw->aq.arq.bal  = I40E_PF_ARQBAL;
71 		hw->aq.arq.bah  = I40E_PF_ARQBAH;
110 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
141 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
160 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
164 	hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
168 		bi = &hw->aq.arq.r.arq_bi[i];
177 		desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
205 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
206 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
261 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
264 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
267 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
338 	wr32(hw, hw->aq.arq.head, 0);
339 	wr32(hw, hw->aq.arq.tail, 0);
343 		wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
346 		wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
348 	wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
349 	wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
352 	wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
355 	reg = rd32(hw, hw->aq.arq.bal);
356 	if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))
442 	if (hw->aq.arq.count > 0) {
455 	hw->aq.arq.next_to_use = 0;
456 	hw->aq.arq.next_to_clean = 0;
474 	hw->aq.arq.count = hw->aq.num_arq_entries;
530 	if (hw->aq.arq.count == 0) {
536 	wr32(hw, hw->aq.arq.head, 0);
537 	wr32(hw, hw->aq.arq.tail, 0);
538 	wr32(hw, hw->aq.arq.len, 0);
539 	wr32(hw, hw->aq.arq.bal, 0);
540 	wr32(hw, hw->aq.arq.bah, 0);
542 	hw->aq.arq.count = 0; /* to indicate uninitialized queue */
564 	hw->aq.arq.next_to_use = 0;
565 	hw->aq.arq.next_to_clean = 0;
1035 	u16 ntc = hw->aq.arq.next_to_clean;
1049 	if (hw->aq.arq.count == 0) {
1058 		ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1060 		ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
1068 	desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
1088 			    hw->aq.arq.r.arq_bi[desc_idx].va,
1099 	bi = &hw->aq.arq.r.arq_bi[ntc];
1110 	wr32(hw, hw->aq.arq.tail, ntc);
1115 	hw->aq.arq.next_to_clean = ntc;
1116 	hw->aq.arq.next_to_use = ntu;
1122 		*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);