Lines Matching refs:reg_val
2237 u32 reg_val;
2241 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2245 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2246 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2251 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2255 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2259 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2265 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2270 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2271 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2272 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2273 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2274 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2278 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2711 u16 reg_slice, reg_val;
2735 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2737 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2739 reg_val);
2755 u32 reg_val;
2760 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2764 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2765 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2766 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2767 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2772 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2775 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2784 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2905 u32 reg_val;
2910 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2913 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2916 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2923 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2926 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2927 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2928 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2931 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2936 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2939 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2940 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2941 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2944 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2951 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2954 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2955 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2956 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2957 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2960 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2976 u32 reg_val;
2985 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2989 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2990 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2995 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2998 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3007 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3134 u32 reg_val;
3139 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3142 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3143 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3144 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3147 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3154 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3157 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3158 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3161 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3168 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3171 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3174 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3181 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3184 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3187 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3980 u32 pause, asm_dir, reg_val;
4034 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4037 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4040 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4042 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4045 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);