dev/ixgbe/ixgbe_dcb_82599.c

121 	u32 reg = 0;
130 	reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
131 	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
139 	reg = 0;
141 		reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
143 	IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
149 		reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
151 		reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
154 			reg |= IXGBE_RTRPT4C_LSP;
156 		IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
163 	reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
164 	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
179 	u32 reg, max_credits;
191 		reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
192 		reg |= refill[i];
193 		reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
196 			reg |= IXGBE_RTTDT2C_GSP;
199 			reg |= IXGBE_RTTDT2C_LSP;
201 		IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
208 	reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
209 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
225 	u32 reg;
232 	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
235 	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
243 	reg = 0;
245 		reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
247 	IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
251 		reg = refill[i];
252 		reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
253 		reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
256 			reg |= IXGBE_RTTPT2C_GSP;
259 			reg |= IXGBE_RTTPT2C_LSP;
261 		IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
268 	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
270 	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
285 	u32 i, j, fcrtl, reg;
292 	reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
293 	reg |= IXGBE_MFLCN_DPF;
300 	reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
303 		reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
306 		reg |= IXGBE_MFLCN_RPFCE;
308 	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
328 			reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
339 			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
343 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
352 	reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
354 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
372 	u32 reg = 0;
394 			reg = 0x01010101 * (i / 4);
395 			IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
408 				reg = 0x00000000;
410 				reg = 0x01010101;
412 				reg = 0x02020202;
414 				reg = 0x03030303;
416 				reg = 0x04040404;
418 				reg = 0x05050505;
420 				reg = 0x06060606;
422 				reg = 0x07070707;
423 			IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
439 			reg = 0x01010101 * (i / 8);
440 			IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
453 				reg = 0x00000000;
455 				reg = 0x01010101;
457 				reg = 0x02020202;
459 				reg = 0x03030303;
460 			IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
498 	u32 reg;
502 	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
503 	reg |= IXGBE_RTTDCS_ARBDIS;
504 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
506 	reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
509 		switch (reg & IXGBE_MRQC_MRQE_MASK) {
513 			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
519 			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
528 			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
535 			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
538 			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
541 	IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
545 		reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
548 		reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
550 			reg |= IXGBE_MTQC_VT_ENA;
552 	IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
560 	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
561 	reg &= ~IXGBE_RTTDCS_ARBDIS;
562 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
565 	reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
566 	reg |= IXGBE_SECTX_DCB;
567 	IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);