dev/ixgbe/ixgbe_dcb_82598.c

121 	u32 reg = 0;
126 	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
127 	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
129 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
131 	reg &= ~IXGBE_RMCS_ARBDIS;
133 	reg |= IXGBE_RMCS_RRM;
135 	reg |= IXGBE_RMCS_DFP;
137 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
144 		reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
147 			reg |= IXGBE_RT2CR_LSP;
149 		IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
152 	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
153 	reg |= IXGBE_RDRXCTL_RDMTS_1_2;
154 	reg |= IXGBE_RDRXCTL_MPBEN;
155 	reg |= IXGBE_RDRXCTL_MCEN;
156 	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
158 	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
160 	reg &= ~IXGBE_RXCTRL_DMBYPS;
161 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
177 	u32 reg, max_credits;
180 	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
183 	reg &= ~IXGBE_DPMCS_ARBDIS;
184 	reg |= IXGBE_DPMCS_TSOEF;
187 	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
189 	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
194 		reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
195 		reg |= refill[i];
196 		reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
199 			reg |= IXGBE_TDTQ2TCCR_GSP;
202 			reg |= IXGBE_TDTQ2TCCR_LSP;
204 		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
221 	u32 reg;
224 	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
226 	reg &= ~IXGBE_PDPMCS_ARBDIS;
228 	reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
230 	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
234 		reg = refill[i];
235 		reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
236 		reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
239 			reg |= IXGBE_TDPT2TCCR_GSP;
242 			reg |= IXGBE_TDPT2TCCR_LSP;
244 		IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
248 	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
249 	reg |= IXGBE_DTXCTL_ENDBUBD;
250 	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
264 	u32 fcrtl, reg;
268 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
269 	reg &= ~IXGBE_RMCS_TFCE_802_3X;
270 	reg |= IXGBE_RMCS_TFCE_PRIORITY;
271 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
274 	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
275 	reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
278 		reg |= IXGBE_FCTRL_RPFCE;
280 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
291 		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
293 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
297 	reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
299 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
316 	u32 reg = 0;
320 	/* Receive Queues stats setting -  8 queues per statistics reg */
322 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
323 		reg |= ((0x1010101) * j);
324 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
325 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
326 		reg |= ((0x1010101) * j);
327 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
329 	/* Transmit Queues stats setting -  4 queues per statistics reg*/
331 		reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
332 		reg |= ((0x1010101) * i);
333 		IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);