dev/ixgbe/if_ixv.c

158 TUNABLE_INT("hw.ixv.num_queues", &ixv_num_queues);
167 TUNABLE_INT("hw.ixv.enable_aim", &ixv_enable_aim);
171 TUNABLE_INT("hw.ixv.rx_process_limit", &ixv_rx_process_limit);
175 TUNABLE_INT("hw.ixv.tx_process_limit", &ixv_tx_process_limit);
179 TUNABLE_INT("hw.ixv.flow_control", &ixv_flow_control);
188 TUNABLE_INT("hw.ixv.hdr_split", &ixv_header_split);
196 TUNABLE_INT("hw.ixv.txd", &ixv_txd);
200 TUNABLE_INT("hw.ixv.rxd", &ixv_rxd);
204 TUNABLE_INT("hw.ixv.enable_legacy_tx", &ixv_enable_legacy_tx);
275 	struct ixgbe_hw *hw;
289 	adapter->hw.back = adapter;
290 	hw = &adapter->hw;
320 	hw->vendor_id = pci_get_vendor(dev);
321 	hw->device_id = pci_get_device(dev);
322 	hw->revision_id = pci_get_revid(dev);
323 	hw->subsystem_vendor_id = pci_get_subvendor(dev);
324 	hw->subsystem_device_id = pci_get_subdevice(dev);
327 	switch (hw->device_id) {
329 		hw->mac.type = ixgbe_mac_82599_vf;
332 		hw->mac.type = ixgbe_mac_X540_vf;
335 		hw->mac.type = ixgbe_mac_X550_vf;
338 		hw->mac.type = ixgbe_mac_X550EM_x_vf;
341 		hw->mac.type = ixgbe_mac_X550EM_a_vf;
354 	error = ixgbe_init_ops_vf(hw);
362 	ixgbe_init_mbx_params_vf(hw);
367 	error = hw->mac.ops.reset_hw(hw);
378 	error = hw->mac.ops.init_hw(hw);
387 	error = ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_12);
396 	if (!ixv_check_ether_addr(hw->mac.addr)) {
401 		bcopy(addr, hw->mac.addr, sizeof(addr));
402 		bcopy(addr, hw->mac.perm_addr, sizeof(addr));
551  *   by the driver as a hw/sw initialization routine to get
561 	struct ixgbe_hw *hw = &adapter->hw;
566 	hw->adapter_stopped = FALSE;
567 	hw->mac.ops.stop_adapter(hw);
571 	hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
574 	bcopy(IF_LLADDR(adapter->ifp), hw->mac.addr,
576 	hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, 1);
586 	hw->mac.ops.reset_hw(hw);
587 	error = ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_12);
634 	IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_EICS_RTX_QUEUE);
637 	IXGBE_WRITE_REG(hw, IXGBE_VTEITR(adapter->vector), IXGBE_LINK_ITR);
643 	hw->mac.ops.check_link(hw, &adapter->link_speed, &adapter->link_up,
666 	struct ixgbe_hw *hw = &adapter->hw;
671 	IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
677 	struct ixgbe_hw *hw = &adapter->hw;
682 	IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, mask);
689 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_VTEICS, mask);
734 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_VTEITR(que->msix),
785 	struct ixgbe_hw *hw = &adapter->hw;
791 	reg = IXGBE_READ_REG(hw, IXGBE_VTEICS);
793 	IXGBE_WRITE_REG(hw, IXGBE_VTEICR, reg);
799 	IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_EIMS_OTHER);
915 	adapter->hw.mac.ops.update_mc_addr_list(&adapter->hw, update_ptr, mcnt,
929 ixv_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq)
1061 	struct ixgbe_hw *hw = &adapter->hw;
1073 	hw->mac.ops.reset_hw(hw);
1074 	adapter->hw.adapter_stopped = FALSE;
1075 	hw->mac.ops.stop_adapter(hw);
1079 	hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1106 	adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1213 	ether_ifattach(ifp, adapter->hw.mac.addr);
1256 	struct ixgbe_hw *hw = &adapter->hw;
1264 		txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
1266 		IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
1269 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_VFTDH(i), 0);
1270 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_VFTDT(i), 0);
1276 		IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
1278 		IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i), (tdba >> 32));
1279 		IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
1281 		txctrl = IXGBE_READ_REG(hw, IXGBE_VFDCA_TXCTRL(i));
1283 		IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), txctrl);
1286 		txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
1288 		IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
1301 	struct ixgbe_hw *hw = &adapter->hw;
1317 		IXGBE_WRITE_REG(hw, IXGBE_VFRSSRK(i), rss_key[i]);
1342 			IXGBE_WRITE_REG(hw, IXGBE_VFRETA(i >> 2), reta);
1387 	IXGBE_WRITE_REG(hw, IXGBE_VFMRQC, mrqc);
1398 	struct ixgbe_hw *hw = &adapter->hw;
1416 	IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
1419 	if (ixgbevf_rlpml_set_vf(hw, adapter->max_frame_size) != 0) {
1428 		rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
1430 		IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
1432 			if (IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)) &
1440 		IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
1442 		IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i), (rdba >> 32));
1443 		IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
1447 		IXGBE_WRITE_REG(hw, IXGBE_VFRDH(rxr->me), 0);
1448 		IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me), 0);
1451 		reg = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(i));
1456 		IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), reg);
1463 		IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
1465 			if (IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)) &
1496 			IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me), t);
1499 			IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me),
1503 	rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1518 	IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1529 	struct ixgbe_hw *hw = &adapter->hw;
1543 		ctrl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
1545 		IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), ctrl);
1572 			while (hw->mac.ops.set_vfta(hw, vid, 0, TRUE, FALSE)) {
1644 	struct ixgbe_hw *hw = &adapter->hw;
1649 	IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
1653 	IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, mask);
1658 	IXGBE_WRITE_FLUSH(hw);
1669 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_VTEIAC, 0);
1670 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_VTEIMC, ~0);
1671 	IXGBE_WRITE_FLUSH(&adapter->hw);
1687 	struct ixgbe_hw *hw = &adapter->hw;
1693 		ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
1696 		IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar);
1699 		ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(entry >> 1));
1702 		IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(entry >> 1), ivar);
1720 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_VTEITR(que->msix),
1786 	struct ixgbe_hw *hw = &adapter->hw;
1788 	adapter->stats.vf.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC);
1789 	adapter->stats.vf.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB);
1791 	    (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32);
1793 	adapter->stats.vf.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC);
1794 	adapter->stats.vf.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB);
1796 	    (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32);
1798 	adapter->stats.vf.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC);
1809 	u32 current = IXGBE_READ_REG(hw, reg);          \
1819 	u64 cur_lsb = IXGBE_READ_REG(hw, lsb);          \
1820 	u64 cur_msb = IXGBE_READ_REG(hw, msb);          \
1835 	struct ixgbe_hw *hw = &adapter->hw;
1961 	struct ixgbe_hw *hw = &adapter->hw;
1968 	    IXGBE_READ_REG(hw, IXGBE_ERRBC));
2028 	switch (adapter->hw.mac.type) {
2323 	if (adapter->hw.mac.type == ixgbe_mac_82599_vf) {
2399 	adapter->hw.mac.ops.check_link(&adapter->hw, &adapter->link_speed,
2410 	adapter->hw.mac.get_link_status = TRUE;
2412 	adapter->hw.mac.ops.check_link(&adapter->hw, &adapter->link_speed,