Lines Matching refs:sched_base
7423 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
7435 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
7438 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
7484 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
7499 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
7702 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
7703 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
7719 iwn_mem_write(sc, sc->sched_base +
7722 iwn_mem_write(sc, sc->sched_base +
7762 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
7763 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
7782 iwn_mem_write(sc, sc->sched_base +
7785 iwn_mem_write(sc, sc->sched_base +