dev/iwn/if_iwn.c

3165 	uint16_t ssn;
3181 	ssn = 0;
3184 		ssn = tap->txa_start & 0xfff;
3187 	for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) {
3209 		ops->ampdu_tx_stop(sc, qid, tid, ssn);
3661 	uint16_t ssn;
3751 	ssn = 0;
3754 		ssn = tap->txa_start & 0xfff;
3780 		ops->ampdu_tx_stop(sc, qid, tid, ssn);
7233 	uint16_t ssn;
7240 	ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START);
7247 	node.addba_ssn = htole16(ssn);
7249 	    wn->id, tid, ssn);
7374 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n",
7412     int qid, uint8_t tid, uint16_t ssn)
7430 	sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7431 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7432 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
7451 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
7460 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7461 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
7473     int qid, uint8_t tid, uint16_t ssn)
7494 	sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7495 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7496 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
7511 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
7523 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7524 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);