dev/iwi/if_iwi.c

340 		error = iwi_alloc_tx_ring(sc, &sc->txq[i], IWI_TX_RING_COUNT,
462 	iwi_free_tx_ring(sc, &sc->txq[0]);
463 	iwi_free_tx_ring(sc, &sc->txq[1]);
464 	iwi_free_tx_ring(sc, &sc->txq[2]);
465 	iwi_free_tx_ring(sc, &sc->txq[3]);
1606 iwi_tx_intr(struct iwi_softc *sc, struct iwi_tx_ring *txq)
1611 	hw = CSR_READ_4(sc, txq->csr_ridx);
1613 	while (txq->next != hw) {
1614 		data = &txq->data[txq->next];
1615 		DPRINTFN(15, ("tx done idx=%u\n", txq->next));
1616 		bus_dmamap_sync(txq->data_dmat, data->map,
1618 		bus_dmamap_unload(txq->data_dmat, data->map);
1622 		txq->queued--;
1623 		txq->next = (txq->next + 1) % IWI_TX_RING_COUNT;
1691 		iwi_tx_intr(sc, &sc->txq[0]);
1694 		iwi_tx_intr(sc, &sc->txq[1]);
1697 		iwi_tx_intr(sc, &sc->txq[2]);
1700 		iwi_tx_intr(sc, &sc->txq[3]);
1775 	struct iwi_tx_ring *txq = &sc->txq[ac];
1858 	data = &txq->data[txq->cur];
1859 	desc = &txq->desc[txq->cur];
1865 	error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1883 		error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map,
1917 	bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1918 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1920 	DPRINTFN(5, ("sending data frame txq=%u idx=%u len=%u nseg=%u\n",
1921 	    ac, txq->cur, le16toh(desc->len), nsegs));
1923 	txq->queued++;
1924 	txq->cur = (txq->cur + 1) % IWI_TX_RING_COUNT;
1925 	CSR_WRITE_4(sc, txq->csr_widx, txq->cur);
1973 		if (sc->txq[ac].queued > IWI_TX_RING_COUNT - 8) {
3122 	CSR_WRITE_4(sc, IWI_CSR_TX1_BASE, sc->txq[0].physaddr);
3123 	CSR_WRITE_4(sc, IWI_CSR_TX1_SIZE, sc->txq[0].count);
3124 	CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq[0].cur);
3126 	CSR_WRITE_4(sc, IWI_CSR_TX2_BASE, sc->txq[1].physaddr);
3127 	CSR_WRITE_4(sc, IWI_CSR_TX2_SIZE, sc->txq[1].count);
3128 	CSR_WRITE_4(sc, IWI_CSR_TX2_WIDX, sc->txq[1].cur);
3130 	CSR_WRITE_4(sc, IWI_CSR_TX3_BASE, sc->txq[2].physaddr);
3131 	CSR_WRITE_4(sc, IWI_CSR_TX3_SIZE, sc->txq[2].count);
3132 	CSR_WRITE_4(sc, IWI_CSR_TX3_WIDX, sc->txq[2].cur);
3134 	CSR_WRITE_4(sc, IWI_CSR_TX4_BASE, sc->txq[3].physaddr);
3135 	CSR_WRITE_4(sc, IWI_CSR_TX4_SIZE, sc->txq[3].count);
3136 	CSR_WRITE_4(sc, IWI_CSR_TX4_WIDX, sc->txq[3].cur);
3205 	iwi_reset_tx_ring(sc, &sc->txq[0]);
3206 	iwi_reset_tx_ring(sc, &sc->txq[1]);
3207 	iwi_reset_tx_ring(sc, &sc->txq[2]);
3208 	iwi_reset_tx_ring(sc, &sc->txq[3]);