dev/isp/isp.c

196 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_HOST_INT);
197 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
198 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_PAUSE);
200 		ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
241 			ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS);
242 			ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET);
243 			ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS);
244 			ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL);
245 			ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS);
426 		ISP_WRITE(isp, BIU_ICR, BIU_ICR_SOFT_RESET);
435 		ISP_WRITE(isp, CDMA_CONTROL, DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT);
436 		ISP_WRITE(isp, DDMA_CONTROL, DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT);
443 		ISP_WRITE(isp, BIU2400_CSR, BIU2400_DMA_STOP|(3 << 4));
458 		ISP_WRITE(isp, BIU2400_CSR, BIU2400_SOFT_RESET|BIU2400_DMA_STOP|(3 << 4));
475 		ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET);
484 		ISP_WRITE(isp, CDMA2100_CONTROL, DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
485 		ISP_WRITE(isp, TDMA2100_CONTROL, DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
486 		ISP_WRITE(isp, RDMA2100_CONTROL, DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
519 		ISP_WRITE(isp, BIU_CONF1, 0);
521 		ISP_WRITE(isp, BIU2100_CSR, 0);
528 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_RESET);
529 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_RELEASE);
530 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RESET);
532 		ISP_WRITE(isp, HCCR, HCCR_CMD_RESET);
534 		ISP_WRITE(isp, BIU_SEMA, 0);
568 					ISP_WRITE(isp, RISC_MTR, 0x1313);
569 					ISP_WRITE(isp, HCCR, HCCR_CMD_STEP);
572 				ISP_WRITE(isp, RISC_MTR, 0x1212);
577 			ISP_WRITE(isp, RISC_EMB, DUAL_BANK);
579 			ISP_WRITE(isp, RISC_MTR, 0x1212);
581 		ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
583 		ISP_WRITE(isp, RISC_MTR2100, 0x1212);
585 			ISP_WRITE(isp, HCCR, HCCR_2X00_DISABLE_PARITY_PAUSE);
587 		ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
610 	ISP_WRITE(isp, isp->isp_rqstinrp, 0);
611 	ISP_WRITE(isp, isp->isp_rqstoutrp, 0);
612 	ISP_WRITE(isp, isp->isp_respinrp, 0);
613 	ISP_WRITE(isp, isp->isp_respoutrp, 0);
616 			ISP_WRITE(isp, BIU2400_PRI_REQINP, 0);
617 			ISP_WRITE(isp, BIU2400_PRI_REQOUTP, 0);
619 		ISP_WRITE(isp, BIU2400_ATIO_RSPINP, 0);
620 		ISP_WRITE(isp, BIU2400_ATIO_RSPOUTP, 0);
625 		ISP_WRITE(isp, HCCR, PCI_HCCR_CMD_BIOS);
1298 			ISP_WRITE(isp, BIU2400_ICR, 0);
1299 			ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_PAUSE);
1301 			ISP_WRITE(isp, BIU_ICR, 0);
1302 			ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
1303 			ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS);
1304 			ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET);
1305 			ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS);
1306 			ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL);
1307 			ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS);
1310 		ISP_WRITE(isp, BIU_ICR, 0);
1311 		ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
1354 		ISP_WRITE(isp, RISC_MTR, 0x1313);
5090 		ISP_WRITE(isp, BIU2400_ATIO_RSPOUTP, optr);
5428 		ISP_WRITE(isp, isp->isp_respoutrp, optr);
7081 			ISP_WRITE(isp, MBOX_OFF(box), mbp->param[box]);
7098 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_SET_HOST_INT);
7100 		ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT);
7571 				ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS);
7572 				ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET);
7573 				ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS);
7574 				ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL);
7575 				ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS);
7710 	ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT);
7712 	ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK);
7741 		ISP_WRITE(isp, BIU_NVRAM, bit);
7744 		ISP_WRITE(isp, BIU_NVRAM, bit | BIU_NVRAM_CLOCK);
7747 		ISP_WRITE(isp, BIU_NVRAM, bit);
7758 		ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK);
7765 		ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT);
7769 	ISP_WRITE(isp, BIU_NVRAM, 0);
7787 	ISP_WRITE(isp, BIU2400_FLASH_ADDR, base | addr);