isci/scil/scic_sds_controller.h

61  *        the core controller object.
95  * the controller object.
176     * This field is the driver timer object handler used to time the controller
182     * This field is the current set of state handlers assigned to this controller
189     * core controller object.
201     * core controller object.
206     * This field contains the port configuration agent for this controller.
212     * controller object.  There is one dummy port object also contained within
213     * this controller object.
219     * controller object.
225     * for this controller object.  This table is used as a fast lookup of device
233     * this controller object.  This table is used as a fast lookup of the io
286     * This field is the array of physical memory requiremets for this controller
299     * controller object writes this value to the hardware after processing the
336     * data utilized by the core controller.
341     * This field records the fact that the controller has encountered a fatal
347     * This field specifies that the controller should ignore
355     * This field is the driver timer handle for controller phy request startup.
356     * On controller start the controller will start each PHY individually in
382     * This is the controller index for this controller object.
387     * This field is the PCI revision code for the controller object.
392     * This field saves the current interrupt coalescing number of the controller.
426                      struct SCIC_SDS_CONTROLLER *controller,
432                      struct SCIC_SDS_CONTROLLER    * controller,
475  * This is a helper macro that sets the state handlers for the controller
483  * controller object
490  * controller object.
492 #define scic_sds_controller_get_port_configuration_agent(controller) \
493    (&(controller)->port_agent)
504  * This macro writes to the smu_register for this controller
506 #define smu_register_write(controller, reg, value) \
507    scic_sds_pci_write_smu_dword((controller), &(reg), (value))
510  * This macro reads the smu_register for this controller
512 #define smu_register_read(controller, reg) \
513    scic_sds_pci_read_smu_dword((controller), &(reg))
516  * This mcaro writes the scu_register for this controller
518 #define scu_register_write(controller, reg, value) \
519    scic_sds_pci_write_scu_dword((controller), &(reg), (value))
522  * This macro reads the scu_register for this controller
524 #define scu_register_read(controller, reg) \
525    scic_sds_pci_read_scu_dword((controller), &(reg))
529     * This macro writes to the lex_register for this controller.
531    #define lex_register_write(controller, reg, value) \
532       scic_cb_pci_write_dword((controller), (reg), (value))
535     * This macro reads from the lex_register for this controller.
537    #define lex_register_read(controller, reg) \
538       scic_cb_pci_read_dword((controller), (reg))
542  * This macro returns the protocol engine group for this controller object.
545 #define scic_sds_controller_get_protocol_engine_group(controller) 0
585  * This macro will set the bit in the invalid phy mask for this controller
589 #define scic_sds_controller_set_invalid_phy(controller, phy) \
590    ((controller)->invalid_phy_mask |= (1 << (phy)->phy_index))
593  * This macro will clear the bit in the invalid phy mask for this controller
597 #define scic_sds_controller_clear_invalid_phy(controller, phy) \
598    ((controller)->invalid_phy_mask &= ~(1 << (phy)->phy_index))
678    void *controller
807    SCI_CONTROLLER_HANDLE_T controller