dev/hatm/if_hatmvar.h

180 #define TPD_SET_USED(SC, I) do {				\
181 	(SC)->tpd_used[(I) / 8] |= (1 << ((I) % 8));		\
184 #define TPD_CLR_USED(SC, I) do {				\
185 	(SC)->tpd_used[(I) / 8] &= ~(1 << ((I) % 8));		\
188 #define TPD_TST_USED(SC, I) ((SC)->tpd_used[(I) / 8] & (1 << ((I) % 8)))
190 #define TPD_ADDR(SC, I) ((struct tpd *)((char *)sc->tpds.base +	\
472 #define READ4(SC,OFF)	bus_space_read_4(SC->memt, SC->memh, (OFF))
473 #define READ2(SC,OFF)	bus_space_read_2(SC->memt, SC->memh, (OFF))
474 #define READ1(SC,OFF)	bus_space_read_1(SC->memt, SC->memh, (OFF))
476 #define WRITE4(SC,OFF,VAL) bus_space_write_4(SC->memt, SC->memh, (OFF), (VAL))
477 #define WRITE2(SC,OFF,VAL) bus_space_write_2(SC->memt, SC->memh, (OFF), (VAL))
478 #define WRITE1(SC,OFF,VAL) bus_space_write_1(SC->memt, SC->memh, (OFF), (VAL))
480 #define BARRIER_R(SC) bus_space_barrier(SC->memt, SC->memh, 0, HE_REGO_END, \
482 #define BARRIER_W(SC) bus_space_barrier(SC->memt, SC->memh, 0, HE_REGO_END, \
484 #define BARRIER_RW(SC) bus_space_barrier(SC->memt, SC->memh, 0, HE_REGO_END, \
487 #define READ_SUNI(SC,OFF) READ4(SC, HE_REGO_SUNI + 4 * (OFF))
488 #define WRITE_SUNI(SC,OFF,VAL) WRITE4(SC, HE_REGO_SUNI + 4 * (OFF), (VAL))
490 #define READ_LB4(SC,OFF)						\
492 	WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF));				\
493 	WRITE4(SC, HE_REGO_LB_MEM_ACCESS,				\
495 	while((READ4(SC, HE_REGO_LB_MEM_ACCESS) & HE_REGM_LB_MEM_HNDSHK))\
497 	READ4(SC, HE_REGO_LB_MEM_DATA);					\
499 #define WRITE_LB4(SC,OFF,VAL)						\
501 	WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF));				\
502 	WRITE4(SC, HE_REGO_LB_MEM_DATA, (VAL));				\
503 	WRITE4(SC, HE_REGO_LB_MEM_ACCESS,				\
505 	while((READ4(SC, HE_REGO_LB_MEM_ACCESS) & HE_REGM_LB_MEM_HNDSHK))\
509 #define WRITE_MEM4(SC,OFF,VAL,SPACE)					\
511 	WRITE4(SC, HE_REGO_CON_DAT, (VAL));				\
512 	WRITE4(SC, HE_REGO_CON_CTL,					\
514 	while((READ4(SC, HE_REGO_CON_CTL) & HE_REGM_CON_STATUS) != 0)	\
518 #define READ_MEM4(SC,OFF,SPACE)					\
520 	WRITE4(SC, HE_REGO_CON_CTL,					\
522 	while((READ4(SC, HE_REGO_CON_CTL) & HE_REGM_CON_STATUS) != 0)	\
524 	READ4(SC, HE_REGO_CON_DAT);					\
527 #define WRITE_TCM4(SC,OFF,VAL) WRITE_MEM4(SC,(OFF),(VAL),HE_REGM_CON_TCM)
528 #define WRITE_RCM4(SC,OFF,VAL) WRITE_MEM4(SC,(OFF),(VAL),HE_REGM_CON_RCM)
529 #define WRITE_MBOX4(SC,OFF,VAL) WRITE_MEM4(SC,(OFF),(VAL),HE_REGM_CON_MBOX)
531 #define READ_TCM4(SC,OFF) READ_MEM4(SC,(OFF),HE_REGM_CON_TCM)
532 #define READ_RCM4(SC,OFF) READ_MEM4(SC,(OFF),HE_REGM_CON_RCM)
533 #define READ_MBOX4(SC,OFF) READ_MEM4(SC,(OFF),HE_REGM_CON_MBOX)
535 #define WRITE_TCM(SC,OFF,BYTES,VAL) 					\
536 	WRITE_MEM4(SC,(OFF) | ((~(BYTES) & 0xf) << HE_REGS_CON_DIS),	\
538 #define WRITE_RCM(SC,OFF,BYTES,VAL) 					\
539 	WRITE_MEM4(SC,(OFF) | ((~(BYTES) & 0xf) << HE_REGS_CON_DIS),	\
542 #define READ_TSR(SC,CID,NR)						\
546 		_v = READ_TCM4(SC, HE_REGO_TSRA(0,CID,NR));		\
548 		_v = READ_TCM4(SC, HE_REGO_TSRB((SC)->tsrb,CID,(NR-8)));\
550 		_v = READ_TCM4(SC, HE_REGO_TSRC((SC)->tsrc,CID,(NR-12)));\
552 		_v = READ_TCM4(SC, HE_REGO_TSRD((SC)->tsrd,CID));	\
557 #define WRITE_TSR(SC,CID,NR,BEN,VAL)					\
560 		WRITE_TCM(SC, HE_REGO_TSRA(0,CID,NR),BEN,VAL);		\
562 		WRITE_TCM(SC, HE_REGO_TSRB((SC)->tsrb,CID,(NR-8)),BEN,VAL);\
564 		WRITE_TCM(SC, HE_REGO_TSRC((SC)->tsrc,CID,(NR-12)),BEN,VAL);\
566 		WRITE_TCM(SC, HE_REGO_TSRD((SC)->tsrd,CID),BEN,VAL);	\
570 #define READ_RSR(SC,CID,NR)						\
574 		_v = READ_RCM4(SC, HE_REGO_RSRA(0,CID,NR));		\
576 		_v = READ_RCM4(SC, HE_REGO_RSRB((SC)->rsrb,CID,(NR-8)));\
581 #define WRITE_RSR(SC,CID,NR,BEN,VAL)					\
584 		WRITE_RCM(SC, HE_REGO_RSRA(0,CID,NR),BEN,VAL);		\
586 		WRITE_RCM(SC, HE_REGO_RSRB((SC)->rsrb,CID,(NR-8)),BEN,VAL);\
591 #define DBG(SC, FL, PRINT) do {						\
592 	if((SC)->debug & DBG_##FL) { 					\
593 		if_printf((SC)->ifp, "%s: ", __func__);			\
615 #define DBG(SC, FL, PRINT)