dev/hatm/if_hatm_tx.c

135 	t->cid = 0;
170     u_int cid)
215 		sc->tpdrq.tpdrq[sc->tpdrq.tail].cid = cid;
299 			tpd->cid = arg->first->cid;
338 	if (hatm_queue_tpds(arg->sc, tpd_cnt, tpd_list, arg->first->cid)) {
358 	u_int cid;
399 		cid = HE_CID(arg.vpi, arg.vci);
400 		arg.vcc = sc->vccs[cid];
458 		tpd->cid = cid;
505 	struct hevcc *vcc = sc->vccs[tpd->cid];
507 	DBG(sc, TX, ("tx_complete cid=%#x flags=%#x", tpd->cid, flags));
514 			hatm_tx_vcc_closed(sc, tpd->cid);
516 				hatm_vcc_closed(sc, tpd->cid);
533 		    HE_VPI(tpd->cid), HE_VCI(tpd->cid), 0);
563 hatm_tx_vcc_can_open(struct hatm_softc *sc, u_int cid, struct hevcc *vcc)
571 	v = READ_TSR(sc, cid, 4);
573 		if_printf(sc->ifp, "cid=%#x not closed (TSR4)\n", cid);
577 	v = READ_TSR(sc, cid, 0);
579 		if_printf(sc->ifp, "cid=%#x not closed (TSR0=%#x)\n",
580 		    cid, v);
658 hatm_tx_vcc_open(struct hatm_softc *sc, u_int cid)
660 	struct hevcc *vcc = sc->vccs[cid];
681 		WRITE_TSR(sc, cid, 0, 0xf, tsr0);
682 		WRITE_TSR(sc, cid, 4, 0xf, tsr4);
683 		WRITE_TSR(sc, cid, 1, 0xf, (atmf << HE_REGS_TSR1_PCR));
684 		WRITE_TSR(sc, cid, 2, 0xf, (atmf << HE_REGS_TSR2_ACR));
685 		WRITE_TSR(sc, cid, 9, 0xf, HE_REGM_TSR9_INIT);
686 		WRITE_TSR(sc, cid, 3, 0xf, 0);
687 		WRITE_TSR(sc, cid, 5, 0xf, 0);
688 		WRITE_TSR(sc, cid, 6, 0xf, 0);
689 		WRITE_TSR(sc, cid, 7, 0xf, 0);
690 		WRITE_TSR(sc, cid, 8, 0xf, 0);
691 		WRITE_TSR(sc, cid, 10, 0xf, 0);
692 		WRITE_TSR(sc, cid, 11, 0xf, 0);
693 		WRITE_TSR(sc, cid, 12, 0xf, 0);
694 		WRITE_TSR(sc, cid, 13, 0xf, 0);
695 		WRITE_TSR(sc, cid, 14, 0xf, 0);
708 		WRITE_TSR(sc, cid, 1, 0xf, (atmf << HE_REGS_TSR1_PCR));
709 		WRITE_TSR(sc, cid, 2, 0xf, (atmf << HE_REGS_TSR2_ACR));
710 		WRITE_TSR(sc, cid, 3, 0xf, 0);
711 		WRITE_TSR(sc, cid, 5, 0xf, 0);
712 		WRITE_TSR(sc, cid, 6, 0xf, 0);
713 		WRITE_TSR(sc, cid, 7, 0xf, 0);
714 		WRITE_TSR(sc, cid, 8, 0xf, 0);
715 		WRITE_TSR(sc, cid, 10, 0xf, 0);
716 		WRITE_TSR(sc, cid, 11, 0xf, 0);
717 		WRITE_TSR(sc, cid, 12, 0xf, 0);
718 		WRITE_TSR(sc, cid, 13, 0xf, 0);
719 		WRITE_TSR(sc, cid, 14, 0xf, 0);
720 		WRITE_TSR(sc, cid, 4, 0xf, tsr4);
721 		WRITE_TSR(sc, cid, 9, 0xf, HE_REGM_TSR9_INIT);
722 		WRITE_TSR(sc, cid, 0, 0xf, tsr0);
733 		WRITE_TSR(sc, cid, 0, 0xf, tsr0);
734 		WRITE_TSR(sc, cid, 4, 0xf, tsr4);
736 		WRITE_TSR(sc, cid, 1, 0xf,
739 		WRITE_TSR(sc, cid, 2, 0xf,
741 		WRITE_TSR(sc, cid, 3, 0xf,
745 		WRITE_TSR(sc, cid, 5, 0xf, 0);
746 		WRITE_TSR(sc, cid, 6, 0xf, 0);
747 		WRITE_TSR(sc, cid, 7, 0xf, 0);
748 		WRITE_TSR(sc, cid, 8, 0xf, 0);
749 		WRITE_TSR(sc, cid, 10, 0xf, 0);
750 		WRITE_TSR(sc, cid, 12, 0xf, 0);
751 		WRITE_TSR(sc, cid, 14, 0xf, 0);
752 		WRITE_TSR(sc, cid, 9, 0xf, HE_REGM_TSR9_INIT);
754 		WRITE_TSR(sc, cid, 11, 0xf,
760 		WRITE_TSR(sc, cid, 13, 0xf,
779 hatm_tx_vcc_close(struct hatm_softc *sc, u_int cid)
781 	struct hevcc *vcc = sc->vccs[cid];
785 	WRITE_TSR(sc, cid, 4, 0x8, HE_REGM_TSR4_FLUSH);
790 		WRITE_TSR(sc, cid, 14, 0x8, HE_REGM_TSR14_CBR_DELETE);
794 		WRITE_TSR(sc, cid, 14, 0x4, HE_REGM_TSR14_ABR_CLOSE);
799 		WRITE_TSR(sc, cid, 1, 0xf,
807 	tpd_list[0]->cid = cid;
813 	while (hatm_queue_tpds(sc, 1, tpd_list, cid) != 0) {
821 hatm_tx_vcc_closed(struct hatm_softc *sc, u_int cid)
823 	if (sc->vccs[cid]->param.traffic == ATMIO_TRAFFIC_CBR) {
824 		sc->cbr_bw -= sc->vccs[cid]->param.tparam.pcr;
825 		sc->rate_ctrl[sc->vccs[cid]->rc].refcnt--;