Lines Matching refs:fc
278 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
280 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
298 device_printf(sc->fc.dev, "%s: %d->%d (loop=%d)\n",
323 device_printf(sc->fc.dev, "%s: failed(1).\n", __func__);
334 device_printf(sc->fc.dev, "%s: failed(2).\n", __func__);
341 device_printf(sc->fc.dev,
353 struct fwohci_softc *fc;
363 fc = (struct fwohci_softc *)sc->fc;
372 OWRITE(fc, reg->addr, reg->data);
373 reg->data = OREAD(fc, reg->addr);
380 reg->data = OREAD(fc, reg->addr);
388 dump_dma(fc, *dmach);
389 dump_db(fc, *dmach);
398 reg->data = fwphy_rddata(fc, reg->addr);
404 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
434 sc->fc.mode &= ~FWPHYASYST;
435 sc->fc.nport = reg & FW_PHY_NP;
436 sc->fc.speed = reg & FW_PHY_SPD >> 6;
437 if (sc->fc.speed > MAX_SPEED) {
439 sc->fc.speed, MAX_SPEED);
440 sc->fc.speed = MAX_SPEED;
444 linkspeed[sc->fc.speed], sc->fc.nport);
447 sc->fc.mode |= FWPHYASYST;
448 sc->fc.nport = reg & FW_PHY_NP;
449 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
450 if (sc->fc.speed > MAX_SPEED) {
452 sc->fc.speed, MAX_SPEED);
453 sc->fc.speed = MAX_SPEED;
457 linkspeed[sc->fc.speed], sc->fc.nport);
509 for (i = 0; i < sc->fc.nisodma; i++) {
537 sc->fc.maxrec = sc->fc.speed + 8;
538 if (max_rec != sc->fc.maxrec) {
539 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
541 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
548 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
595 fwohci_set_intr(&sc->fc, 1);
624 sc->fc.nisodma = i;
629 sc->fc.arq = &sc->arrq.xferq;
630 sc->fc.ars = &sc->arrs.xferq;
631 sc->fc.atq = &sc->atrq.xferq;
632 sc->fc.ats = &sc->atrs.xferq;
664 for (i = 0; i < sc->fc.nisodma; i++) {
665 sc->fc.it[i] = &sc->it[i].xferq;
666 sc->fc.ir[i] = &sc->ir[i].xferq;
673 sc->fc.tcode = tinfo;
674 sc->fc.dev = dev;
676 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
678 if (sc->fc.config_rom == NULL) {
684 bzero(&sc->fc.config_rom[0], CROMSIZE);
685 sc->fc.config_rom[1] = 0x31333934;
686 sc->fc.config_rom[2] = 0xf000a002;
687 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
688 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
689 sc->fc.config_rom[5] = 0;
690 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
692 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
697 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
704 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t),
728 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
729 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
731 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
735 sc->fc.ioctl = fwohci_ioctl;
736 sc->fc.cyctimer = fwohci_cyctimer;
737 sc->fc.set_bmr = fwohci_set_bus_manager;
738 sc->fc.ibr = fwohci_ibr;
739 sc->fc.irx_enable = fwohci_irx_enable;
740 sc->fc.irx_disable = fwohci_irx_disable;
742 sc->fc.itx_enable = fwohci_itxbuf_enable;
743 sc->fc.itx_disable = fwohci_itx_disable;
745 sc->fc.irx_post = fwohci_irx_post;
747 sc->fc.irx_post = NULL;
749 sc->fc.itx_post = NULL;
750 sc->fc.timeout = fwohci_timeout;
751 sc->fc.poll = fwohci_poll;
752 sc->fc.set_intr = fwohci_set_intr;
757 sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK,
758 taskqueue_thread_enqueue, &sc->fc.taskqueue);
759 taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq",
765 fw_init(&sc->fc);
780 fwohci_cyctimer(struct firewire_comm *fc)
782 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
792 fwdma_free(&sc->fc, &sc->sid_dma);
793 if (sc->fc.config_rom != NULL)
794 fwdma_free(&sc->fc, &sc->crom_dma);
802 for (i = 0; i < sc->fc.nisodma; i++) {
806 if (sc->fc.taskqueue != NULL) {
807 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset);
808 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid);
809 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma);
810 taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout);
811 taskqueue_free(sc->fc.taskqueue);
812 sc->fc.taskqueue = NULL;
872 FW_GLOCK_ASSERT(&sc->fc);
893 device_printf(sc->fc.dev, "TX queue empty\n");
965 device_printf(sc->fc.dev, "EFBIG.\n");
977 device_printf(sc->fc.dev, "m_getcl failed.\n");
993 device_printf(sc->fc.dev, "%s: maxdesc %d\n", __func__, maxdesc);
1014 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1026 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1038 fwohci_start_atq(struct firewire_comm *fc)
1040 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1041 FW_GLOCK(&sc->fc);
1043 FW_GUNLOCK(&sc->fc);
1048 fwohci_start_ats(struct firewire_comm *fc)
1050 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1051 FW_GLOCK(&sc->fc);
1053 FW_GUNLOCK(&sc->fc);
1067 struct firewire_comm *fc = (struct firewire_comm *)sc;
1087 if (fc->status != FWBUSINIT)
1101 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1166 FW_GLOCK(fc);
1168 FW_GUNLOCK(fc);
1185 FW_GLOCK(fc);
1187 FW_GUNLOCK(fc);
1230 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1240 /*lockarg*/FW_GMTX(&sc->fc),
1252 dbch->am = fwdma_malloc_multiseg(&sc->fc, sizeof(struct fwohcidb),
1295 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1297 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1311 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1313 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1327 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld)
1348 for (dmach = 0; dmach < sc->fc.nisodma; dmach++) {
1408 for (dmach = 0; dmach < sc->fc.nisodma; dmach++) {
1469 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1500 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1502 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1530 FW_GLOCK(fc);
1557 FW_GUNLOCK(fc);
1596 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1597 cycle_match = fwohci_next_cycle(fc, cycle_now);
1612 device_printf(sc->fc.dev,
1621 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1623 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1653 device_printf(fc->dev, "IR DMA no free chunk\n");
1660 FW_GLOCK(fc);
1689 FW_GUNLOCK(fc);
1698 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1724 fwohci_set_intr(&sc->fc, 0);
1732 for (i = 0; i < sc->fc.nisodma; i++) {
1764 for (i = 0; i < sc->fc.nisodma; i++) {
1767 device_printf(sc->fc.dev,
1775 sc->fc.irx_enable(&sc->fc, i);
1780 sc->fc.ibr(&sc->fc);
1789 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1819 struct firewire_comm *fc = (struct firewire_comm *)sc;
1823 FW_GLOCK_ASSERT(fc);
1824 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1825 fc->status = FWBUSRESET;
1829 device_printf(fc->dev, "%s: BUS reset\n", __func__);
1839 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset);
1854 device_printf(fc->dev,
1865 device_printf(fc->dev,
1869 device_printf(fc->dev,
1884 fc->nodeid = node_id & 0x3f;
1885 device_printf(fc->dev, "%s: node_id=0x%08x, SelfID Count=%d, ",
1886 __func__, fc->nodeid, (plen >> 16) & 0xff);
1888 device_printf(fc->dev, "%s: Bus reset failure\n",
1906 fc->status = FWBUSINIT;
1909 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid);
1913 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma);
1921 struct firewire_comm *fc = (struct firewire_comm *)sc;
1925 for (i = 0; i < fc->nisodma; i++) {
1931 device_printf(sc->fc.dev,
1941 for (i = 0; i < fc->nisodma; i++) {
1970 device_printf(fc->dev, "too many cycles lost, "
1981 device_printf(fc->dev, "posted write error\n");
1984 device_printf(fc->dev, "unrecoverable error\n");
1987 device_printf(fc->dev, "phy int\n");
1996 FW_GLOCK(&sc->fc);
1997 fw_busreset(&sc->fc, FWBUSRESET);
1998 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1999 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2000 FW_GUNLOCK(&sc->fc);
2007 struct firewire_comm *fc = &sc->fc;
2019 device_printf(fc->dev, "SID Error\n");
2024 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2030 device_printf(fc->dev, "malloc failed\n");
2041 fw_drain_txq(fc);
2042 fw_sidrcv(fc, buf, plen);
2066 FW_GLOCK_ASSERT(&sc->fc);
2069 if (!bus_child_present(sc->fc.dev))
2071 device_printf(sc->fc.dev, "device physically ejected?\n");
2102 FW_GLOCK(&sc->fc);
2104 FW_GUNLOCK(&sc->fc);
2108 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2110 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2112 FW_GLOCK(fc);
2114 FW_GUNLOCK(fc);
2118 fwohci_set_intr(struct firewire_comm *fc, int enable)
2122 sc = (struct fwohci_softc *)fc;
2124 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2137 struct firewire_comm *fc = &sc->fc;
2144 it = fc->it[dmach];
2147 FW_GLOCK(fc);
2165 device_printf(fc->dev, "0x%08x\n", count);
2169 device_printf(fc->dev,
2176 FW_GUNLOCK(fc);
2185 struct firewire_comm *fc = &sc->fc;
2192 ir = fc->ir[dmach];
2199 FW_GLOCK(fc);
2228 device_printf(fc->dev,
2235 FW_GUNLOCK(fc);
2267 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2274 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2286 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2321 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2454 fwohci_ibr(struct firewire_comm *fc)
2459 device_printf(fc->dev, "Initiate bus reset\n");
2460 sc = (struct fwohci_softc *)fc;
2462 FW_GLOCK(fc);
2467 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2468 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2483 FW_GUNLOCK(fc);
2497 FW_GLOCK_ASSERT(&sc->fc);
2505 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2549 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2700 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2706 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2896 rb.fc = &sc->fc;
2904 if ((sc->fc.status != FWBUSRESET) &&
2905 (sc->fc.status != FWBUSINIT))
2909 device_printf(sc->fc.dev,
2960 device_printf(sc->fc.dev, "AR DMA status=%x, ",