Lines Matching defs:dbch
857 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
874 if (&sc->atrq == dbch) {
876 } else if (&sc->atrs == dbch) {
882 if (dbch->flags & FWOHCI_DBCH_FULL)
885 db_tr = dbch->top;
887 xfer = STAILQ_FIRST(&dbch->xferq.q);
892 if (dbch->xferq.queued == 0) {
896 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
933 if (&sc->atrs == dbch) {
951 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
957 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
982 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
1004 if (dbch->pdb_tr != NULL) {
1005 LAST_DB(dbch->pdb_tr, db);
1008 dbch->xferq.queued++;
1009 dbch->pdb_tr = db_tr;
1011 if (db_tr != dbch->bottom) {
1015 dbch->flags |= FWOHCI_DBCH_FULL;
1019 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1020 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1022 if (dbch->xferq.flag & FWXFERQ_RUNNING) {
1028 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1030 dbch->xferq.flag |= FWXFERQ_RUNNING;
1033 dbch->top = db_tr;
1058 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1069 if (&sc->atrq == dbch) {
1072 } else if (&sc->atrs == dbch) {
1079 tr = dbch->bottom;
1081 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1082 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1083 while (dbch->xferq.queued > 0) {
1091 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1093 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1167 dbch->xferq.queued--;
1173 dbch->bottom = tr;
1174 if (dbch->bottom == dbch->top) {
1176 if (firewire_debug && dbch->xferq.queued > 0)
1182 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1184 dbch->flags &= ~FWOHCI_DBCH_FULL;
1186 fwohci_start(sc, dbch);
1193 fwohci_db_free(struct fwohci_dbch *dbch)
1198 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1201 for (db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1203 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1205 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1206 db_tr->buf, dbch->xferq.psize);
1209 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1211 dbch->ndb = 0;
1212 db_tr = STAILQ_FIRST(&dbch->db_trq);
1213 fwdma_free_multiseg(dbch->am);
1215 STAILQ_INIT(&dbch->db_trq);
1216 dbch->flags &= ~FWOHCI_DBCH_INIT;
1220 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1225 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1235 /*maxsize*/ dbch->xferq.psize,
1236 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1241 &dbch->dmat))
1246 STAILQ_INIT(&dbch->db_trq);
1248 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1252 dbch->am = fwdma_malloc_multiseg(&sc->fc, sizeof(struct fwohcidb),
1253 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1254 if (dbch->am == NULL) {
1260 for (idb = 0; idb < dbch->ndb; idb++) {
1262 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1263 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1267 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1269 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1270 fwohci_db_free(dbch);
1273 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1274 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1275 if (idb % dbch->xferq.bnpacket == 0)
1276 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1278 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1279 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1284 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1285 = STAILQ_FIRST(&dbch->db_trq);
1287 dbch->xferq.queued = 0;
1288 dbch->pdb_tr = NULL;
1289 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1290 dbch->bottom = dbch->top;
1291 dbch->flags = FWOHCI_DBCH_INIT;
1335 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1343 if (!(dbch->xferq.flag & FWXFERQ_EXTBUF)) {
1347 z = dbch->ndesc;
1349 if (&sc->it[dmach] == dbch) {
1358 if (dbch->xferq.flag & FWXFERQ_RUNNING)
1360 dbch->xferq.flag |= FWXFERQ_RUNNING;
1361 for (i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++) {
1362 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1364 db_tr = dbch->top;
1365 for (idb = 0; idb < dbch->ndb; idb++) {
1366 fwohci_add_tx_buf(dbch, db_tr, idb);
1375 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1376 if (((idb + 1) % dbch->xferq.bnpacket) == 0) {
1389 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1394 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1402 z = dbch->ndesc;
1403 if (&sc->arrq == dbch) {
1405 } else if (&sc->arrs == dbch) {
1409 if (&sc->ir[dmach] == dbch) {
1419 if (dbch->xferq.flag & FWXFERQ_STREAM) {
1420 if (dbch->xferq.flag & FWXFERQ_RUNNING)
1423 if (dbch->xferq.flag & FWXFERQ_RUNNING) {
1428 dbch->xferq.flag |= FWXFERQ_RUNNING;
1429 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1430 for (i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++) {
1431 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1433 db_tr = dbch->top;
1434 for (idb = 0; idb < dbch->ndb; idb++) {
1435 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1442 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1443 if (((idb + 1) % dbch->xferq.bnpacket) == 0) {
1455 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1456 dbch->buf_offset = 0;
1457 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1458 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1459 if (dbch->xferq.flag & FWXFERQ_STREAM) {
1462 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1505 struct fwohci_dbch *dbch;
1511 dbch = &sc->it[dmach];
1512 it = &dbch->xferq;
1516 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1517 dbch->ndb = it->bnpacket * it->bnchunk;
1518 dbch->ndesc = 3;
1519 fwohci_db_init(sc, dbch);
1520 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1523 err = fwohci_tx_enable(sc, dbch);
1528 ldesc = dbch->ndesc - 1;
1547 (chunk->start))->bus_addr | dbch->ndesc;
1549 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1550 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1558 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1559 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1578 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1627 struct fwohci_dbch *dbch;
1632 dbch = &sc->ir[dmach];
1633 ir = &dbch->xferq;
1641 dbch->ndb = ir->bnpacket * ir->bnchunk;
1642 dbch->ndesc = 2;
1643 fwohci_db_init(sc, dbch);
1644 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1646 err = fwohci_rx_enable(sc, dbch);
1657 ldesc = dbch->ndesc - 1;
1669 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1682 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1690 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1691 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1710 | dbch->ndesc);
1926 struct fwohci_dbch *dbch;
1929 dbch = &sc->ir[i];
1930 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
2293 struct fwohci_dbch *dbch;
2301 dbch = &sc->atrq;
2304 dbch = &sc->atrs;
2307 dbch = &sc->arrq;
2310 dbch = &sc->arrs;
2313 dbch = &sc->it[ch - ITX_CH];
2316 dbch = &sc->ir[ch - IRX_CH];
2320 if (dbch->ndb == 0) {
2324 pp = dbch->top;
2326 for (idb = 0; idb < dbch->ndb; idb++) {
2333 for (jdb = 0; jdb < dbch->ndesc; jdb++) {
2355 print_db(pp, prev, ch, dbch->ndesc);
2358 print_db(cp, curr, ch, dbch->ndesc);
2361 print_db(np, next, ch, dbch->ndesc);
2490 struct fwohci_dbch *dbch;
2499 dbch = &sc->it[dmach];
2507 for (idb = 0; idb < dbch->xferq.bnpacket; idb++) {
2529 = db[dbch->ndesc - 1].db.desc.depend
2530 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2532 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2533 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2540 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2542 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2555 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2562 it = &dbch->xferq;
2587 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2596 ir = &dbch->xferq;
2597 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2599 db_tr->buf = fwdma_malloc_size(dbch->dmat,
2607 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2688 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2705 if (r > dbch->xferq.psize) {
2715 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2721 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2722 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2723 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2724 dbch->bottom = db_tr;
2731 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2746 if (&sc->arrq == dbch) {
2748 } else if (&sc->arrs == dbch) {
2755 db_tr = dbch->top;
2758 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2759 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2769 len = dbch->xferq.psize - resCount;
2771 if (dbch->pdb_tr == NULL) {
2772 len -= dbch->buf_offset;
2773 ld += dbch->buf_offset;
2776 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2781 if (dbch->pdb_tr != NULL) {
2785 offset = dbch->buf_offset;
2788 buf = dbch->pdb_tr->buf + offset;
2789 rlen = dbch->xferq.psize - offset;
2792 rlen, dbch->buf_offset);
2793 if (dbch->buf_offset < 0) {
2830 dbch->pdb_tr = db_tr;
2831 dbch->buf_offset = - dbch->buf_offset;
2843 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2854 dbch->pdb_tr = db_tr;
2871 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2914 dbch->buf_offset, len,
2923 if (dbch->pdb_tr != NULL) {
2924 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr,
2926 dbch->pdb_tr = NULL;
2933 if (dbch->pdb_tr == NULL) {
2934 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2935 dbch->buf_offset = 0;
2937 if (dbch->pdb_tr != db_tr)
2945 dbch->top = db_tr;
2947 dbch->buf_offset = dbch->xferq.psize - resCount;
2962 dbch->pdb_tr = NULL;
2967 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2973 dbch->top = db_tr;
2974 dbch->buf_offset = dbch->xferq.psize - resCount;