Lines Matching defs:db_tr
497 struct fwohcidb_tr *db_tr;
578 for (i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb;
579 i++, db_tr = STAILQ_NEXT(db_tr, link)) {
580 db_tr->xfer = NULL;
582 for (i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb;
583 i++, db_tr = STAILQ_NEXT(db_tr, link)) {
584 db_tr->xfer = NULL;
827 struct fwohcidb_tr *db_tr;
832 db_tr = (struct fwohcidb_tr *)arg;
833 db = &db_tr->db[db_tr->dbcnt];
845 db_tr->dbcnt++;
866 struct fwohcidb_tr *db_tr;
885 db_tr = dbch->top;
897 db_tr->xfer = xfer;
903 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
927 db = &db_tr->db[0];
945 db_tr->dbcnt = 2;
946 db = &db_tr->db[db_tr->dbcnt];
951 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
953 fwohci_execute_db, db_tr,
957 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
959 fwohci_execute_db2, db_tr,
982 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
985 for (i = 2; i < db_tr->dbcnt; i++)
986 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
990 if (maxdesc < db_tr->dbcnt) {
991 maxdesc = db_tr->dbcnt;
996 LAST_DB(db_tr, db);
1000 STAILQ_NEXT(db_tr, link)->bus_addr);
1003 fsegment = db_tr->dbcnt;
1006 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1009 dbch->pdb_tr = db_tr;
1010 db_tr = STAILQ_NEXT(db_tr, link);
1011 if (db_tr != dbch->bottom) {
1033 dbch->top = db_tr;
1195 struct fwohcidb_tr *db_tr;
1201 for (db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1202 db_tr = STAILQ_NEXT(db_tr, link), idb++) {
1204 db_tr->buf != NULL) {
1205 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1206 db_tr->buf, dbch->xferq.psize);
1207 db_tr->buf = NULL;
1208 } else if (db_tr->dma_map != NULL)
1209 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1212 db_tr = STAILQ_FIRST(&dbch->db_trq);
1214 free(db_tr, M_FW);
1223 struct fwohcidb_tr *db_tr;
1247 db_tr = (struct fwohcidb_tr *)
1256 free(db_tr, M_FW);
1261 db_tr->dbcnt = 0;
1262 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1263 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1267 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1273 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1277 ].start = (caddr_t)db_tr;
1280 ].end = (caddr_t)db_tr;
1282 db_tr++;
1340 struct fwohcidb_tr *db_tr;
1364 db_tr = dbch->top;
1366 fwohci_add_tx_buf(dbch, db_tr, idb);
1367 if (STAILQ_NEXT(db_tr, link) == NULL) {
1370 db = db_tr->db;
1371 ldesc = db_tr->dbcnt - 1;
1373 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1386 db_tr = STAILQ_NEXT(db_tr, link);
1399 struct fwohcidb_tr *db_tr;
1433 db_tr = dbch->top;
1435 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1436 if (STAILQ_NEXT(db_tr, link) == NULL)
1438 db = db_tr->db;
1439 ldesc = db_tr->dbcnt - 1;
1441 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1452 db_tr = STAILQ_NEXT(db_tr, link);
1455 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1628 struct fwohcidb_tr *db_tr;
1667 db_tr = (struct fwohcidb_tr *)(chunk->start);
1668 db_tr->dbcnt = 1;
1669 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1670 chunk->mbuf, fwohci_execute_db2, db_tr,
1672 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
2186 struct fwohcidb_tr *db_tr;
2202 db_tr = (struct fwohcidb_tr *)chunk->end;
2203 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2209 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2211 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2370 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2400 (uintmax_t)db_tr->bus_addr,
2489 struct fwohcidb_tr *db_tr, *fdb_tr;
2502 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2505 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2508 db = db_tr->db;
2509 fp = (struct fw_pkt *)db_tr->buf;
2530 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2535 bulkxfer->end = (caddr_t)db_tr;
2536 db_tr = STAILQ_NEXT(db_tr, link);
2547 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2549 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2555 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2558 struct fwohcidb *db = db_tr->db;
2567 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2568 db_tr->dbcnt = 3;
2587 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2590 struct fwohcidb *db = db_tr->db;
2598 if (db_tr->buf == NULL) {
2599 db_tr->buf = fwdma_malloc_size(dbch->dmat,
2600 &db_tr->dma_map, ir->psize, &dbuf[0],
2602 if (db_tr->buf == NULL)
2605 db_tr->dbcnt = 1;
2607 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2610 db_tr->dbcnt = 0;
2612 dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2613 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2615 dsiz[db_tr->dbcnt] = ir->psize;
2617 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2618 dbuf[db_tr->dbcnt] = fwdma_bus_addr(ir->buf, poffset);
2620 db_tr->dbcnt++;
2622 for (i = 0; i < db_tr->dbcnt; i++) {
2630 ldesc = db_tr->dbcnt - 1;
2716 struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2718 struct fwohcidb *db = &db_tr->db[0];
2724 dbch->bottom = db_tr;
2733 struct fwohcidb_tr *db_tr;
2755 db_tr = dbch->top;
2760 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2761 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2767 db_tr->bus_addr, status, resCount);
2770 ld = (uint8_t *)db_tr->buf;
2776 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2804 bcopy(db_tr->buf, p, rlen);
2830 dbch->pdb_tr = db_tr;
2854 dbch->pdb_tr = db_tr;
2871 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2934 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2937 if (dbch->pdb_tr != db_tr)
2938 printf("pdb_tr != db_tr\n");
2939 db_tr = STAILQ_NEXT(db_tr, link);
2940 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2942 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2945 dbch->top = db_tr;
2967 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2968 db_tr = STAILQ_NEXT(db_tr, link);
2969 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2973 dbch->top = db_tr;