Lines Matching refs:cfg
154 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
158 if (!cfg)
162 switch (cfg->mode) {
168 if (cfg->rxclk_sel)
170 if (cfg->txclk_sel)
176 if (cfg->rxclk_sel)
178 if (cfg->txclk_sel)
191 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
192 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
193 if (cfg->rxclk_delay_en)
195 if (cfg->txclk_delay_en)
198 if (cfg->sgmii_delay_en)
205 if (cfg->rxclk_sel)
207 if (cfg->txclk_sel)
213 if (cfg->pipe_rxclk_sel)
215 if (cfg->rxclk_sel)
217 if (cfg->txclk_sel)
223 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
224 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
225 if (cfg->rxclk_delay_en)
227 if (cfg->txclk_delay_en)
252 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
256 if (!cfg->force_link)
260 t |= cfg->duplex ? AR8X16_PORT_STS_DUPLEX : 0;
261 t |= cfg->rxpause ? AR8X16_PORT_STS_RXFLOW : 0;
262 t |= cfg->txpause ? AR8X16_PORT_STS_TXFLOW : 0;
264 switch (cfg->speed) {
621 device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__);