Lines Matching defs:mphy_ctrl
4110 u32 mphy_ctrl = 0;
4122 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4123 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4128 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4129 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4138 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4141 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4172 u32 mphy_ctrl = 0;
4184 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4185 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4190 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4191 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4201 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4203 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4204 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4206 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4234 u32 mphy_ctrl = 0;
4238 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4239 if (mphy_ctrl & E1000_MPHY_BUSY) {