Lines Matching refs:hw
74 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
86 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
87 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
95 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
99 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
102 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
104 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
105 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
106 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
111 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
114 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
117 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
118 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
121 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
122 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
123 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
124 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
127 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
139 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
141 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
142 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
143 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
145 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
146 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
147 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
192 * @hw: pointer to the HW structure
198 * Assumes the sw/fw/hw semaphore is already acquired.
200 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
223 if (hw->phy.id) {
224 if (hw->phy.id == phy_id)
227 hw->phy.id = phy_id;
228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
235 if (hw->mac.type < e1000_pch_lpt) {
236 hw->phy.ops.release(hw);
237 ret_val = e1000_set_mdio_slow_mode_hv(hw);
239 ret_val = e1000_get_phy_id(hw);
240 hw->phy.ops.acquire(hw);
246 if (hw->mac.type >= e1000_pch_lpt) {
248 if (!(E1000_READ_REG(hw, E1000_FWSM) &
251 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
256 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
267 * @hw: pointer to the HW structure
272 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
279 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
282 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
285 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
288 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
289 E1000_WRITE_FLUSH(hw);
292 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
293 E1000_WRITE_FLUSH(hw);
295 if (hw->mac.type < e1000_pch_lpt) {
302 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
311 * @hw: pointer to the HW structure
316 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
318 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
326 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
331 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
332 e1000_disable_ulp_lpt_lp(hw, TRUE);
334 ret_val = hw->phy.ops.acquire(hw);
344 switch (hw->mac.type) {
348 if (e1000_phy_is_accessible_pchlan(hw))
354 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
366 if (e1000_phy_is_accessible_pchlan(hw))
371 if ((hw->mac.type == e1000_pchlan) &&
375 if (hw->phy.ops.check_reset_block(hw)) {
382 e1000_toggle_lanphypc_pch_lpt(hw);
383 if (hw->mac.type >= e1000_pch_lpt) {
384 if (e1000_phy_is_accessible_pchlan(hw))
390 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
392 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
394 if (e1000_phy_is_accessible_pchlan(hw))
404 hw->phy.ops.release(hw);
408 if (hw->phy.ops.check_reset_block(hw)) {
418 ret_val = e1000_phy_hw_reset_generic(hw);
428 ret_val = hw->phy.ops.check_reset_block(hw);
435 if ((hw->mac.type == e1000_pch2lan) &&
438 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
446 * @hw: pointer to the HW structure
450 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
452 struct e1000_phy_info *phy = &hw->phy;
480 ret_val = e1000_init_phy_workarounds_pchlan(hw);
485 switch (hw->mac.type) {
487 ret_val = e1000_get_phy_id(hw);
500 ret_val = e1000_set_mdio_slow_mode_hv(hw);
503 ret_val = e1000_get_phy_id(hw);
537 * @hw: pointer to the HW structure
541 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
543 struct e1000_phy_info *phy = &hw->phy;
568 ret_val = e1000_determine_phy_address(hw);
572 ret_val = e1000_determine_phy_address(hw);
583 ret_val = e1000_get_phy_id(hw);
628 * @hw: pointer to the HW structure
633 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
635 struct e1000_nvm_info *nvm = &hw->nvm;
636 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
645 if (hw->mac.type >= e1000_pch_spt) {
654 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
660 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
663 if (!hw->flash_address) {
668 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
705 if (hw->mac.type >= e1000_pch_spt) {
721 * @hw: pointer to the HW structure
726 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
728 struct e1000_mac_info *mac = &hw->mac;
733 hw->phy.media_type = e1000_media_type_copper;
758 /* hw initialization */
829 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
836 * @hw: pointer to the HW structure
843 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
850 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
855 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
858 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
866 * @hw: pointer to the HW structure
872 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
876 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
881 * @hw: pointer to the HW structure
887 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
891 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
896 * @hw: pointer to the HW structure
908 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
910 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
916 switch (hw->phy.type) {
931 ret_val = hw->phy.ops.acquire(hw);
935 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
945 ret_val = e1000_read_emi_reg_locked(hw, lpa,
951 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
962 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
975 if (hw->phy.type == e1000_phy_82579) {
976 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
982 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
987 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
991 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
993 hw->phy.ops.release(hw);
1000 * @hw: pointer to the HW structure
1009 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1011 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1012 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1017 ret_val = hw->phy.ops.acquire(hw);
1022 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1028 e1000_write_kmrn_reg_locked(hw,
1037 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1041 e1000_write_kmrn_reg_locked(hw,
1045 hw->phy.ops.release(hw);
1050 if ((hw->phy.revision > 5) || !link ||
1055 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1077 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1082 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1101 * @hw: pointer to the HW structure
1118 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1135 if (!hw->mac.max_frame_size) {
1140 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1147 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1158 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1176 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1177 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1199 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1202 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1204 E1000_WRITE_REG(hw, E1000_SVT, reg);
1207 reg = E1000_READ_REG(hw, E1000_SVCR);
1214 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1221 * @hw: pointer to the HW structure
1226 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1242 svcr = E1000_READ_REG(hw, E1000_SVCR);
1245 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1252 * @hw: pointer to the HW structure
1260 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1267 if ((hw->mac.type < e1000_pch_lpt) ||
1268 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1269 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1270 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1271 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1272 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1275 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1277 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1279 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1288 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1291 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1300 (E1000_READ_REG(hw, E1000_FEXT) &
1305 ret_val = hw->phy.ops.acquire(hw);
1310 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1314 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1317 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1319 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1324 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1325 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1333 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1343 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1349 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1361 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1364 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1366 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1370 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1372 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1373 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1374 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1381 hw->phy.ops.release(hw);
1386 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1393 * @hw: pointer to the HW structure
1406 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1413 if ((hw->mac.type < e1000_pch_lpt) ||
1414 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1415 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1416 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1417 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1418 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1421 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1424 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1427 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1431 while (E1000_READ_REG(hw, E1000_FWSM) &
1443 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1445 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1448 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1450 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1456 ret_val = hw->phy.ops.acquire(hw);
1462 e1000_toggle_lanphypc_pch_lpt(hw);
1465 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1470 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1472 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1476 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1482 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1485 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1487 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1492 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1496 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1499 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1510 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1514 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1517 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1519 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1522 hw->phy.ops.release(hw);
1524 hw->phy.ops.reset(hw);
1531 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1538 * @hw: pointer to the HW structure
1544 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1546 struct e1000_mac_info *mac = &hw->mac;
1566 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1570 if (hw->mac.type == e1000_pchlan) {
1571 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1580 if ((hw->mac.type >= e1000_pch2lan) && link) {
1583 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1584 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1591 } else if (hw->mac.type >= e1000_pch_spt &&
1601 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1603 ret_val = hw->phy.ops.acquire(hw);
1607 if (hw->mac.type == e1000_pch2lan)
1611 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1614 if (hw->mac.type >= e1000_pch_lpt) {
1617 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1624 hw->phy.ops.write_reg_locked(hw,
1629 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1634 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1638 hw->phy.ops.release(hw);
1643 if (hw->mac.type >= e1000_pch_spt) {
1648 ret_val = hw->phy.ops.acquire(hw);
1652 ret_val = hw->phy.ops.read_reg_locked(hw,
1656 hw->phy.ops.release(hw);
1665 hw->phy.ops.write_reg_locked(hw,
1668 hw->phy.ops.release(hw);
1672 ret_val = hw->phy.ops.acquire(hw);
1676 ret_val = hw->phy.ops.write_reg_locked(hw,
1679 hw->phy.ops.release(hw);
1692 if (hw->mac.type >= e1000_pch_lpt) {
1695 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1698 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1702 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1703 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1704 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1705 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1706 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1710 if (hw->mac.type >= e1000_pch_lpt) {
1715 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1721 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1723 if (hw->mac.type >= e1000_pch_lpt) {
1724 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1726 if (hw->mac.type == e1000_pch_spt) {
1728 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1736 if (hw->dev_spec.ich8lan.disable_k1_off == TRUE)
1739 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1747 switch (hw->mac.type) {
1749 ret_val = e1000_k1_workaround_lv(hw);
1754 if (hw->phy.type == e1000_phy_82578) {
1755 ret_val = e1000_link_stall_workaround_hv(hw);
1765 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1768 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1772 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1781 e1000_check_downshift_generic(hw);
1784 if (hw->phy.type > e1000_phy_82579) {
1785 ret_val = e1000_set_eee_pchlan(hw);
1800 mac->ops.config_collision_dist(hw);
1807 ret_val = e1000_config_fc_after_link_up_generic(hw);
1816 * @hw: pointer to the HW structure
1820 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1824 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1825 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1826 switch (hw->mac.type) {
1830 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1837 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1846 * @hw: pointer to the HW structure
1850 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1854 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1861 * @hw: pointer to the HW structure
1865 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1869 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1876 * @hw: pointer to the HW structure
1881 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1888 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1891 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1908 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1911 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1921 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1923 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1930 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1937 * @hw: pointer to the HW structure
1942 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1948 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1952 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1954 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1957 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1964 * @hw: pointer to the HW structure
1970 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1976 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1985 * @hw: pointer to the HW structure
1991 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1997 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2005 * @hw: pointer to the HW structure
2014 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2034 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2035 E1000_WRITE_FLUSH(hw);
2036 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2037 E1000_WRITE_FLUSH(hw);
2044 if (index < (u32) (hw->mac.rar_entry_count)) {
2047 ret_val = e1000_acquire_swflag_ich8lan(hw);
2051 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2052 E1000_WRITE_FLUSH(hw);
2053 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2054 E1000_WRITE_FLUSH(hw);
2056 e1000_release_swflag_ich8lan(hw);
2059 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2060 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2064 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2074 * @hw: pointer to the HW structure
2083 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2103 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2104 E1000_WRITE_FLUSH(hw);
2105 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2106 E1000_WRITE_FLUSH(hw);
2113 if (index < hw->mac.rar_entry_count) {
2114 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2125 ret_val = e1000_acquire_swflag_ich8lan(hw);
2130 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2132 E1000_WRITE_FLUSH(hw);
2133 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2135 E1000_WRITE_FLUSH(hw);
2137 e1000_release_swflag_ich8lan(hw);
2140 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2141 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2153 * @hw: pointer to the HW structure
2160 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2170 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2172 ret_val = hw->phy.ops.acquire(hw);
2176 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2180 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2181 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2182 (u16)(hw->mac.mta_shadow[i] &
2184 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2185 (u16)((hw->mac.mta_shadow[i] >> 16) &
2189 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2192 hw->phy.ops.release(hw);
2197 * @hw: pointer to the HW structure
2203 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2212 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2225 * @hw: pointer to the HW structure
2230 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2233 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2240 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2248 if (hw->phy.type == e1000_phy_i217) {
2261 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2266 * @hw: pointer to the HW structure
2271 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2273 struct e1000_phy_info *phy = &hw->phy;
2286 switch (hw->mac.type) {
2291 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2292 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2308 ret_val = hw->phy.ops.acquire(hw);
2312 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2319 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2320 if ((hw->mac.type < e1000_pch2lan) &&
2324 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2333 if (((hw->mac.type == e1000_pchlan) &&
2335 (hw->mac.type > e1000_pchlan)) {
2341 ret_val = e1000_write_smbus_addr(hw);
2345 data = E1000_READ_REG(hw, E1000_LEDCTL);
2346 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2358 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2363 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2377 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2384 hw->phy.ops.release(hw);
2390 * @hw: pointer to the HW structure
2398 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2402 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2406 if (hw->mac.type != e1000_pchlan)
2410 ret_val = hw->phy.ops.acquire(hw);
2416 if (hw->phy.type == e1000_phy_82578) {
2417 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2432 if (hw->phy.type == e1000_phy_82577) {
2433 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2449 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2456 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2462 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2465 hw->phy.ops.release(hw);
2472 * @hw: pointer to the HW structure
2480 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2490 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2500 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2506 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2507 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2511 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2513 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2514 E1000_WRITE_FLUSH(hw);
2516 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2517 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2518 E1000_WRITE_FLUSH(hw);
2526 * @hw: pointer to the HW structure
2533 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2541 if (hw->mac.type < e1000_pchlan)
2544 ret_val = hw->phy.ops.acquire(hw);
2548 if (hw->mac.type == e1000_pchlan) {
2549 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2554 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2558 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2560 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2583 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2584 !hw->phy.ops.check_reset_block(hw))
2587 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2590 hw->phy.ops.release(hw);
2598 * @hw: pointer to the HW structure
2600 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2607 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2613 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2622 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2629 if (hw->mac.type != e1000_pchlan)
2633 if (hw->phy.type == e1000_phy_82577) {
2634 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2639 if (((hw->phy.type == e1000_phy_82577) &&
2640 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2641 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2643 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2648 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2654 if (hw->phy.type == e1000_phy_82578) {
2658 if (hw->phy.revision < 2) {
2659 e1000_phy_sw_reset_generic(hw);
2660 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2668 ret_val = hw->phy.ops.acquire(hw);
2672 hw->phy.addr = 1;
2673 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2674 hw->phy.ops.release(hw);
2681 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2686 ret_val = hw->phy.ops.acquire(hw);
2689 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2692 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2698 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2700 hw->phy.ops.release(hw);
2707 * @hw: pointer to the HW structure
2709 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2717 ret_val = hw->phy.ops.acquire(hw);
2720 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2725 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2726 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2727 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2729 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2732 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2733 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2735 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2740 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2743 hw->phy.ops.release(hw);
2767 * @hw: pointer to the HW structure
2770 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2779 if (hw->mac.type < e1000_pch2lan)
2783 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2784 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2793 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2797 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2800 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2808 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2813 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2816 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2819 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2821 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2823 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2825 ret_val = e1000_read_kmrn_reg_generic(hw,
2830 ret_val = e1000_write_kmrn_reg_generic(hw,
2835 ret_val = e1000_read_kmrn_reg_generic(hw,
2842 ret_val = e1000_write_kmrn_reg_generic(hw,
2849 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2852 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2855 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2857 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2860 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2863 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2866 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2869 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2870 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2876 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2878 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2880 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2882 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2884 ret_val = e1000_read_kmrn_reg_generic(hw,
2889 ret_val = e1000_write_kmrn_reg_generic(hw,
2894 ret_val = e1000_read_kmrn_reg_generic(hw,
2901 ret_val = e1000_write_kmrn_reg_generic(hw,
2908 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2910 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2913 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2915 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2918 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2921 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2924 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2927 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2928 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2935 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2943 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2949 if (hw->mac.type != e1000_pch2lan)
2953 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2957 ret_val = hw->phy.ops.acquire(hw);
2961 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2965 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2967 hw->phy.ops.release(hw);
2974 * @hw: pointer to the HW structure
2979 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2986 if (hw->mac.type != e1000_pch2lan)
2990 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
3001 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
3006 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3012 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3015 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3024 * @hw: pointer to the HW structure
3030 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3036 if (hw->mac.type < e1000_pch2lan)
3039 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3046 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3051 * @hw: pointer to the HW structure
3056 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3064 data = E1000_READ_REG(hw, E1000_STATUS);
3077 data = E1000_READ_REG(hw, E1000_STATUS);
3079 E1000_WRITE_REG(hw, E1000_STATUS, data);
3084 * @hw: pointer to the HW structure
3086 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3093 if (hw->phy.ops.check_reset_block(hw))
3100 switch (hw->mac.type) {
3102 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3107 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3116 if (hw->mac.type >= e1000_pchlan) {
3117 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3119 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3123 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3128 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3130 if (hw->mac.type == e1000_pch2lan) {
3132 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3135 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
3139 ret_val = hw->phy.ops.acquire(hw);
3142 ret_val = e1000_write_emi_reg_locked(hw,
3145 hw->phy.ops.release(hw);
3153 * @hw: pointer to the HW structure
3159 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3166 if ((hw->mac.type == e1000_pch2lan) &&
3167 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3168 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3170 ret_val = e1000_phy_hw_reset_generic(hw);
3174 return e1000_post_phy_reset_ich8lan(hw);
3179 * @hw: pointer to the HW structure
3185 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3188 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3194 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3203 if (!hw->phy.ops.check_reset_block(hw))
3206 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3211 * @hw: pointer to the HW structure
3222 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3224 struct e1000_phy_info *phy = &hw->phy;
3234 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3238 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3246 if (hw->mac.type == e1000_ich8lan)
3247 e1000_gig_downshift_workaround_ich8lan(hw);
3250 ret_val = phy->ops.read_reg(hw,
3256 ret_val = phy->ops.write_reg(hw,
3263 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3274 ret_val = phy->ops.read_reg(hw,
3281 ret_val = phy->ops.write_reg(hw,
3287 ret_val = phy->ops.read_reg(hw,
3294 ret_val = phy->ops.write_reg(hw,
3307 * @hw: pointer to the HW structure
3318 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3320 struct e1000_phy_info *phy = &hw->phy;
3327 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3331 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3342 ret_val = phy->ops.read_reg(hw,
3349 ret_val = phy->ops.write_reg(hw,
3355 ret_val = phy->ops.read_reg(hw,
3362 ret_val = phy->ops.write_reg(hw,
3372 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3380 if (hw->mac.type == e1000_ich8lan)
3381 e1000_gig_downshift_workaround_ich8lan(hw);
3384 ret_val = phy->ops.read_reg(hw,
3391 ret_val = phy->ops.write_reg(hw,
3401 * @hw: pointer to the HW structure
3407 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3410 struct e1000_nvm_info *nvm = &hw->nvm;
3419 switch (hw->mac.type) {
3429 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3441 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3457 eecd = E1000_READ_REG(hw, E1000_EECD);
3474 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3485 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3503 * @hw: pointer to the HW structure
3510 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3513 struct e1000_nvm_info *nvm = &hw->nvm;
3514 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3531 nvm->ops.acquire(hw);
3533 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3552 e1000_read_flash_dword_ich8lan(hw,
3567 e1000_read_flash_dword_ich8lan(hw,
3585 nvm->ops.release(hw);
3596 * @hw: pointer to the HW structure
3603 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3606 struct e1000_nvm_info *nvm = &hw->nvm;
3607 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3622 nvm->ops.acquire(hw);
3624 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3638 ret_val = e1000_read_flash_word_ich8lan(hw,
3647 nvm->ops.release(hw);
3658 * @hw: pointer to the HW structure
3663 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3670 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3678 /* Clear FCERR and DAEL in hw status by writing 1 */
3681 if (hw->mac.type >= e1000_pch_spt)
3682 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3685 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3701 if (hw->mac.type >= e1000_pch_spt)
3702 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3705 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3715 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3728 if (hw->mac.type >= e1000_pch_spt)
3729 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3732 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3744 * @hw: pointer to the HW structure
3749 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3758 if (hw->mac.type >= e1000_pch_spt)
3759 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3761 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3764 if (hw->mac.type >= e1000_pch_spt)
3765 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3768 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3772 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3786 * @hw: pointer to the HW structure
3793 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3804 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3809 * @hw: pointer to the HW structure
3816 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3827 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3832 * @hw: pointer to the HW structure
3838 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3847 if (hw->mac.type >= e1000_pch_spt)
3850 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3862 * @hw: pointer to the HW structure
3869 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3884 hw->nvm.flash_base_addr);
3889 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3892 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3897 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3898 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3900 ret_val = e1000_flash_cycle_ich8lan(hw,
3909 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3921 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3938 * @hw: pointer to the HW structure
3944 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3956 hw->mac.type < e1000_pch_spt)
3959 hw->nvm.flash_base_addr);
3964 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3970 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3978 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3980 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3982 ret_val = e1000_flash_cycle_ich8lan(hw,
3991 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3999 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4016 * @hw: pointer to the HW structure
4023 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4026 struct e1000_nvm_info *nvm = &hw->nvm;
4027 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4038 nvm->ops.acquire(hw);
4045 nvm->ops.release(hw);
4052 * @hw: pointer to the HW structure
4061 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4063 struct e1000_nvm_info *nvm = &hw->nvm;
4064 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4071 ret_val = e1000_update_nvm_checksum_generic(hw);
4078 nvm->ops.acquire(hw);
4084 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4093 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4099 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4108 ret_val = e1000_read_flash_dword_ich8lan(hw,
4141 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4164 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4170 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4184 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4190 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4202 nvm->ops.release(hw);
4208 nvm->ops.reload(hw);
4221 * @hw: pointer to the HW structure
4230 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4232 struct e1000_nvm_info *nvm = &hw->nvm;
4233 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4240 ret_val = e1000_update_nvm_checksum_generic(hw);
4247 nvm->ops.acquire(hw);
4253 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4262 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4268 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4276 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4298 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4305 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4326 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4331 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4343 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4355 nvm->ops.release(hw);
4361 nvm->ops.reload(hw);
4374 * @hw: pointer to the HW structure
4380 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4394 switch (hw->mac.type) {
4407 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4413 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4416 ret_val = hw->nvm.ops.update(hw);
4421 return e1000_validate_nvm_checksum_generic(hw);
4426 * @hw: pointer to the HW structure
4433 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4445 if (hw->mac.type >= e1000_pch_spt) {
4454 hw->nvm.flash_base_addr);
4459 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4465 if (hw->mac.type >= e1000_pch_spt)
4467 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4470 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4479 if (hw->mac.type >= e1000_pch_spt)
4480 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4483 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4486 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4493 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4499 e1000_flash_cycle_ich8lan(hw,
4509 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4524 * @hw: pointer to the HW structure
4530 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4541 if (hw->mac.type >= e1000_pch_spt) {
4546 hw->nvm.flash_base_addr);
4550 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4557 if (hw->mac.type >= e1000_pch_spt)
4558 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4562 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4572 if (hw->mac.type >= e1000_pch_spt)
4573 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4576 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4579 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4581 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4586 ret_val = e1000_flash_cycle_ich8lan(hw,
4597 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4613 * @hw: pointer to the HW structure
4619 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4626 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4631 * @hw: pointer to the HW structure
4638 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4649 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4656 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4668 * @hw: pointer to the HW structure
4675 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4683 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4690 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4702 * @hw: pointer to the HW structure
4708 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4710 struct e1000_nvm_info *nvm = &hw->nvm;
4722 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4724 /* Determine HW Sector size: Read BERASE bits of hw flash status
4759 flash_linear_addr = hw->nvm.flash_base_addr;
4767 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4772 * Cycle field in hw flash control
4774 if (hw->mac.type >= e1000_pch_spt)
4776 E1000_READ_FLASH_REG(hw,
4780 E1000_READ_FLASH_REG16(hw,
4784 if (hw->mac.type >= e1000_pch_spt)
4785 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4788 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4796 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4799 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4807 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4822 * @hw: pointer to the HW structure
4829 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4835 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4849 * @hw: pointer to the HW structure
4860 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4862 struct e1000_mac_info *mac = &hw->mac;
4871 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4875 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4923 * @hw: pointer to the HW structure
4928 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4930 struct e1000_bus_info *bus = &hw->bus;
4935 ret_val = e1000_get_bus_info_pcie_generic(hw);
4950 * @hw: pointer to the HW structure
4955 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4957 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4967 ret_val = e1000_disable_pcie_master_generic(hw);
4972 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4978 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4979 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4980 E1000_WRITE_FLUSH(hw);
4985 if (hw->mac.type == e1000_ich8lan) {
4987 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4989 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4992 if (hw->mac.type == e1000_pchlan) {
4994 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
5004 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5006 if (!hw->phy.ops.check_reset_block(hw)) {
5016 if ((hw->mac.type == e1000_pch2lan) &&
5017 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5018 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
5020 ret_val = e1000_acquire_swflag_ich8lan(hw);
5022 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5027 if (hw->mac.type == e1000_pch2lan) {
5028 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5031 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5035 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
5038 ret_val = hw->phy.ops.get_cfg_done(hw);
5042 ret_val = e1000_post_phy_reset_ich8lan(hw);
5051 if (hw->mac.type == e1000_pchlan)
5052 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5054 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5055 E1000_READ_REG(hw, E1000_ICR);
5057 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5059 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5066 * @hw: pointer to the HW structure
5076 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5078 struct e1000_mac_info *mac = &hw->mac;
5085 e1000_initialize_hw_bits_ich8lan(hw);
5088 ret_val = mac->ops.id_led_init(hw);
5094 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5099 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5105 if (hw->phy.type == e1000_phy_82578) {
5106 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5108 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5109 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5115 ret_val = mac->ops.setup_link(hw);
5118 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5123 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5124 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5129 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5138 e1000_set_pcie_no_snoop_generic(hw, snoop);
5140 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5142 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5149 e1000_clear_hw_cntrs_ich8lan(hw);
5156 * @hw: pointer to the HW structure
5161 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5168 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5171 if (hw->mac.type >= e1000_pchlan)
5173 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5176 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5178 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5181 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5183 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5186 reg = E1000_READ_REG(hw, E1000_TARC(0));
5187 if (hw->mac.type == e1000_ich8lan)
5190 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5193 reg = E1000_READ_REG(hw, E1000_TARC(1));
5194 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5199 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5202 if (hw->mac.type == e1000_ich8lan) {
5203 reg = E1000_READ_REG(hw, E1000_STATUS);
5205 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5211 reg = E1000_READ_REG(hw, E1000_RFCTL);
5217 if (hw->mac.type == e1000_ich8lan)
5219 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5222 if (hw->mac.type >= e1000_pch_lpt) {
5223 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5225 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5227 reg = E1000_READ_REG(hw, E1000_CTRL);
5229 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5237 * @hw: pointer to the HW structure
5245 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5251 if (hw->phy.ops.check_reset_block(hw))
5258 if (hw->fc.requested_mode == e1000_fc_default)
5259 hw->fc.requested_mode = e1000_fc_full;
5264 hw->fc.current_mode = hw->fc.requested_mode;
5267 hw->fc.current_mode);
5270 ret_val = hw->mac.ops.setup_physical_interface(hw);
5274 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5275 if ((hw->phy.type == e1000_phy_82578) ||
5276 (hw->phy.type == e1000_phy_82579) ||
5277 (hw->phy.type == e1000_phy_i217) ||
5278 (hw->phy.type == e1000_phy_82577)) {
5279 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5281 ret_val = hw->phy.ops.write_reg(hw,
5283 hw->fc.pause_time);
5288 return e1000_set_fc_watermarks_generic(hw);
5293 * @hw: pointer to the HW structure
5299 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5307 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5310 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5316 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5320 ret_val = e1000_read_kmrn_reg_generic(hw,
5326 ret_val = e1000_write_kmrn_reg_generic(hw,
5332 switch (hw->phy.type) {
5334 ret_val = e1000_copper_link_setup_igp(hw);
5340 ret_val = e1000_copper_link_setup_m88(hw);
5346 ret_val = e1000_copper_link_setup_82577(hw);
5351 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5358 switch (hw->phy.mdix) {
5370 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5379 return e1000_setup_copper_link_generic(hw);
5384 * @hw: pointer to the HW structure
5390 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5397 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5400 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5402 ret_val = e1000_copper_link_setup_82577(hw);
5406 return e1000_setup_copper_link_generic(hw);
5411 * @hw: pointer to the HW structure
5419 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5426 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5430 if ((hw->mac.type == e1000_ich8lan) &&
5431 (hw->phy.type == e1000_phy_igp_3) &&
5433 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5441 * @hw: pointer to the HW structure
5454 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5456 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5471 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5477 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5481 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5490 hw->phy.ops.reset(hw);
5494 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5497 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5502 e1000_gig_downshift_workaround_ich8lan(hw);
5510 * @hw: pointer to the HW structure
5516 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5519 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5523 if (hw->mac.type != e1000_ich8lan) {
5535 * @hw: pointer to the HW structure
5543 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5551 if (hw->phy.type != e1000_phy_igp_3)
5557 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5560 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5565 if (hw->mac.type == e1000_ich8lan)
5566 e1000_gig_downshift_workaround_ich8lan(hw);
5569 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5571 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5575 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5581 reg = E1000_READ_REG(hw, E1000_CTRL);
5582 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5589 * @hw: pointer to the HW structure
5597 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5604 if ((hw->mac.type != e1000_ich8lan) ||
5605 (hw->phy.type == e1000_phy_ife))
5608 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5613 ret_val = e1000_write_kmrn_reg_generic(hw,
5619 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5625 * @hw: pointer to the HW structure
5637 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5639 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5645 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5648 if (hw->phy.type == e1000_phy_i217) {
5649 u16 phy_reg, device_id = hw->device_id;
5655 (hw->mac.type >= e1000_pch_spt)) {
5656 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5658 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5662 ret_val = hw->phy.ops.acquire(hw);
5670 e1000_read_emi_reg_locked(hw,
5684 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5689 hw->phy.ops.read_reg_locked(hw,
5693 hw->phy.ops.write_reg_locked(hw,
5706 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5709 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5712 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5718 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5720 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5723 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5725 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5731 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5733 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5736 hw->phy.ops.release(hw);
5739 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5741 if (hw->mac.type == e1000_ich8lan)
5742 e1000_gig_downshift_workaround_ich8lan(hw);
5744 if (hw->mac.type >= e1000_pchlan) {
5745 e1000_oem_bits_config_ich8lan(hw, FALSE);
5748 if (hw->mac.type == e1000_pchlan)
5749 e1000_phy_hw_reset_generic(hw);
5751 ret_val = hw->phy.ops.acquire(hw);
5754 e1000_write_smbus_addr(hw);
5755 hw->phy.ops.release(hw);
5763 * @hw: pointer to the HW structure
5771 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5776 if (hw->mac.type < e1000_pch2lan)
5779 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5790 if (hw->phy.type == e1000_phy_i217) {
5793 ret_val = hw->phy.ops.acquire(hw);
5800 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5802 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5804 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5809 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5814 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5817 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5820 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5825 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5829 hw->phy.ops.release(hw);
5837 * @hw: pointer to the HW structure
5841 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5845 if (hw->phy.type == e1000_phy_ife)
5846 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5849 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5855 * @hw: pointer to the HW structure
5859 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5863 if (hw->phy.type == e1000_phy_ife)
5864 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5867 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5873 * @hw: pointer to the HW structure
5877 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5881 if (hw->phy.type == e1000_phy_ife)
5882 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5885 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5891 * @hw: pointer to the HW structure
5895 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5899 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5900 (u16)hw->mac.ledctl_mode1);
5905 * @hw: pointer to the HW structure
5909 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5913 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5914 (u16)hw->mac.ledctl_default);
5919 * @hw: pointer to the HW structure
5923 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5925 u16 data = (u16)hw->mac.ledctl_mode2;
5933 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5946 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5951 * @hw: pointer to the HW structure
5955 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5957 u16 data = (u16)hw->mac.ledctl_mode1;
5965 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5978 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5983 * @hw: pointer to the HW structure
5993 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
6001 e1000_get_cfg_done_generic(hw);
6004 if (hw->mac.type >= e1000_ich10lan) {
6005 e1000_lan_init_done_ich8lan(hw);
6007 ret_val = e1000_get_auto_rd_done_generic(hw);
6019 status = E1000_READ_REG(hw, E1000_STATUS);
6021 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6026 if (hw->mac.type <= e1000_ich9lan) {
6027 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6028 (hw->phy.type == e1000_phy_igp_3)) {
6029 e1000_phy_init_script_igp3(hw);
6032 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6044 * @hw: pointer to the HW structure
6049 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6052 if (!(hw->mac.ops.check_mng_mode(hw) ||
6053 hw->phy.ops.check_reset_block(hw)))
6054 e1000_power_down_phy_copper(hw);
6061 * @hw: pointer to the HW structure
6066 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6073 e1000_clear_hw_cntrs_base_generic(hw);
6075 E1000_READ_REG(hw, E1000_ALGNERRC);
6076 E1000_READ_REG(hw, E1000_RXERRC);
6077 E1000_READ_REG(hw, E1000_TNCRS);
6078 E1000_READ_REG(hw, E1000_CEXTERR);
6079 E1000_READ_REG(hw, E1000_TSCTC);
6080 E1000_READ_REG(hw, E1000_TSCTFC);
6082 E1000_READ_REG(hw, E1000_MGTPRC);
6083 E1000_READ_REG(hw, E1000_MGTPDC);
6084 E1000_READ_REG(hw, E1000_MGTPTC);
6086 E1000_READ_REG(hw, E1000_IAC);
6087 E1000_READ_REG(hw, E1000_ICRXOC);
6090 if ((hw->phy.type == e1000_phy_82578) ||
6091 (hw->phy.type == e1000_phy_82579) ||
6092 (hw->phy.type == e1000_phy_i217) ||
6093 (hw->phy.type == e1000_phy_82577)) {
6094 ret_val = hw->phy.ops.acquire(hw);
6097 ret_val = hw->phy.ops.set_page(hw,
6101 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6102 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6103 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6104 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6105 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6106 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6107 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6108 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6109 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6110 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6111 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6112 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6113 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6114 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6116 hw->phy.ops.release(hw);