dev/e1000/e1000_82575.c

331 	struct e1000_nvm_info *nvm = &hw->nvm;
351 	nvm->word_size = 1 << size;
353 		nvm->opcode_bits = 8;
354 		nvm->delay_usec = 1;
356 		switch (nvm->override) {
358 			nvm->page_size = 32;
359 			nvm->address_bits = 16;
362 			nvm->page_size = 8;
363 			nvm->address_bits = 8;
366 			nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
367 			nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
371 		if (nvm->word_size == (1 << 15))
372 			nvm->page_size = 128;
374 		nvm->type = e1000_nvm_eeprom_spi;
376 		nvm->type = e1000_nvm_flash_hw;
380 	nvm->ops.acquire = e1000_acquire_nvm_82575;
381 	nvm->ops.release = e1000_release_nvm_82575;
382 	if (nvm->word_size < (1 << 15))
383 		nvm->ops.read = e1000_read_nvm_eerd;
385 		nvm->ops.read = e1000_read_nvm_spi;
387 	nvm->ops.write = e1000_write_nvm_spi;
388 	nvm->ops.validate = e1000_validate_nvm_checksum_generic;
389 	nvm->ops.update = e1000_update_nvm_checksum_generic;
390 	nvm->ops.valid_led_default = e1000_valid_led_default_82575;
395 		nvm->ops.validate = e1000_validate_nvm_checksum_82580;
396 		nvm->ops.update = e1000_update_nvm_checksum_82580;
400 		nvm->ops.validate = e1000_validate_nvm_checksum_i350;
401 		nvm->ops.update = e1000_update_nvm_checksum_i350;
538 	hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
1685 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1931 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
2436 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2589 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2626 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2634 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2660 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2700 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2709 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,