Lines Matching refs:hw
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51 static void e1000_release_phy_82575(struct e1000_hw *hw);
52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
55 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
56 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
57 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
106 static void e1000_i2c_start(struct e1000_hw *hw);
107 static void e1000_i2c_stop(struct e1000_hw *hw);
108 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
109 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
110 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
111 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
112 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
113 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
127 * @hw: pointer to the HW structure
132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
139 switch (hw->mac.type) {
142 reg = E1000_READ_REG(hw, E1000_MDIC);
150 reg = E1000_READ_REG(hw, E1000_MDICNFG);
161 * @hw: pointer to the HW structure
163 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
165 struct e1000_phy_info *phy = &hw->phy;
174 if (hw->phy.media_type != e1000_media_type_copper) {
191 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
193 if (e1000_sgmii_active_82575(hw)) {
201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
202 e1000_reset_mdicnfg_82580(hw);
204 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
208 switch (hw->mac.type) {
227 ret_val = e1000_get_phy_id_82575(hw);
256 ret_val = phy->ops.write_reg(hw,
262 ret_val = phy->ops.read_reg(hw,
272 hw->mac.ops.check_for_link =
276 ret_val = e1000_initialize_M88E1512_phy(hw);
281 ret_val = e1000_initialize_M88E1543_phy(hw);
327 * @hw: pointer to the HW structure
329 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
331 struct e1000_nvm_info *nvm = &hw->nvm;
332 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
352 if (hw->mac.type < e1000_i210) {
393 switch (hw->mac.type) {
412 * @hw: pointer to the HW structure
414 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
416 struct e1000_mac_info *mac = &hw->mac;
417 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
422 e1000_get_media_type_82575(hw);
426 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
450 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
461 /* hw initialization */
470 (hw->phy.media_type == e1000_media_type_copper)
484 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
495 if (hw->mac.type >= e1000_82580)
522 hw->mac.ops.set_lan_id(hw);
529 * @hw: pointer to the HW structure
533 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
537 hw->mac.ops.init_params = e1000_init_mac_params_82575;
538 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
539 hw->phy.ops.init_params = e1000_init_phy_params_82575;
540 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
545 * @hw: pointer to the HW structure
549 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
555 if (hw->bus.func == E1000_FUNC_1)
557 else if (hw->bus.func == E1000_FUNC_2)
559 else if (hw->bus.func == E1000_FUNC_3)
562 return hw->mac.ops.acquire_swfw_sync(hw, mask);
567 * @hw: pointer to the HW structure
571 static void e1000_release_phy_82575(struct e1000_hw *hw)
577 if (hw->bus.func == E1000_FUNC_1)
579 else if (hw->bus.func == E1000_FUNC_2)
581 else if (hw->bus.func == E1000_FUNC_3)
584 hw->mac.ops.release_swfw_sync(hw, mask);
589 * @hw: pointer to the HW structure
596 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
608 ret_val = hw->phy.ops.acquire(hw);
612 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
614 hw->phy.ops.release(hw);
622 * @hw: pointer to the HW structure
629 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
641 ret_val = hw->phy.ops.acquire(hw);
645 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
647 hw->phy.ops.release(hw);
655 * @hw: pointer to the HW structure
660 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
662 struct e1000_phy_info *phy = &hw->phy;
671 if (hw->mac.type == e1000_i354)
672 e1000_get_phy_id(hw);
681 if (!e1000_sgmii_active_82575(hw)) {
683 ret_val = e1000_get_phy_id(hw);
687 if (e1000_sgmii_uses_mdio_82575(hw)) {
688 switch (hw->mac.type) {
691 mdic = E1000_READ_REG(hw, E1000_MDIC);
700 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
709 ret_val = e1000_get_phy_id(hw);
714 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
715 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
717 E1000_WRITE_FLUSH(hw);
725 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
746 ret_val = e1000_get_phy_id(hw);
750 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
758 * @hw: pointer to the HW structure
762 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
765 struct e1000_phy_info *phy = &hw->phy;
776 if (!(hw->phy.ops.write_reg))
783 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
787 ret_val = hw->phy.ops.commit(hw);
792 ret_val = e1000_initialize_M88E1512_phy(hw);
799 * @hw: pointer to the HW structure
810 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
812 struct e1000_phy_info *phy = &hw->phy;
818 if (!(hw->phy.ops.read_reg))
821 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
827 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
833 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
836 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
842 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
851 ret_val = phy->ops.read_reg(hw,
858 ret_val = phy->ops.write_reg(hw,
864 ret_val = phy->ops.read_reg(hw,
871 ret_val = phy->ops.write_reg(hw,
885 * @hw: pointer to the HW structure
896 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
898 struct e1000_phy_info *phy = &hw->phy;
903 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
925 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
931 * @hw: pointer to the HW structure
943 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
945 struct e1000_phy_info *phy = &hw->phy;
950 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
972 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
978 * @hw: pointer to the HW structure
985 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
991 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
999 if (hw->mac.type == e1000_i350) {
1000 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1004 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1010 if (hw->mac.type == e1000_82580) {
1011 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1014 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1020 ret_val = e1000_acquire_nvm_generic(hw);
1022 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1030 * @hw: pointer to the HW structure
1035 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1039 e1000_release_nvm_generic(hw);
1041 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1046 * @hw: pointer to the HW structure
1052 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1063 if (e1000_get_hw_semaphore_generic(hw)) {
1068 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1076 e1000_put_hw_semaphore_generic(hw);
1088 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1090 e1000_put_hw_semaphore_generic(hw);
1098 * @hw: pointer to the HW structure
1104 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1110 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1113 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1115 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1117 e1000_put_hw_semaphore_generic(hw);
1122 * @hw: pointer to the HW structure
1130 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1137 if (hw->bus.func == E1000_FUNC_1)
1139 else if (hw->bus.func == E1000_FUNC_2)
1141 else if (hw->bus.func == E1000_FUNC_3)
1144 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1153 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1154 (hw->phy.type == e1000_phy_igp_3))
1155 e1000_phy_init_script_igp3(hw);
1162 * @hw: pointer to the HW structure
1170 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1177 if (hw->phy.media_type != e1000_media_type_copper)
1178 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1181 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1189 * @hw: pointer to the HW structure
1194 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1201 if (hw->phy.media_type != e1000_media_type_copper) {
1202 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1209 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1217 ret_val = e1000_config_fc_after_link_up_generic(hw);
1221 ret_val = e1000_check_for_copper_link_generic(hw);
1229 * @hw: pointer to the HW structure
1233 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1235 struct e1000_phy_info *phy = &hw->phy;
1243 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1247 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1255 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1259 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1267 if (port && (hw->dev_spec._82575.media_port != port)) {
1268 hw->dev_spec._82575.media_port = port;
1269 hw->dev_spec._82575.media_changed = TRUE;
1274 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1277 e1000_check_for_link_82575(hw);
1279 e1000_check_for_link_82575(hw);
1281 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1291 * @hw: pointer to the HW structure
1293 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1299 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1300 !e1000_sgmii_active_82575(hw))
1304 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1306 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1309 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1311 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1314 E1000_WRITE_FLUSH(hw);
1320 * @hw: pointer to the HW structure
1327 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1330 struct e1000_mac_info *mac = &hw->mac;
1341 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1365 status = E1000_READ_REG(hw, E1000_STATUS);
1386 * @hw: pointer to the HW structure
1391 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1397 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1398 !e1000_sgmii_active_82575(hw))
1401 if (!e1000_enable_mng_pass_thru(hw)) {
1403 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1405 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1408 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1410 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1413 E1000_WRITE_FLUSH(hw);
1422 * @hw: pointer to the HW structure
1426 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1437 ret_val = e1000_disable_pcie_master_generic(hw);
1442 ret_val = e1000_set_pcie_completion_timeout(hw);
1447 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1449 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1450 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1451 E1000_WRITE_FLUSH(hw);
1455 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1458 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1460 ret_val = e1000_get_auto_rd_done_generic(hw);
1471 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1472 e1000_reset_init_script_82575(hw);
1475 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1476 E1000_READ_REG(hw, E1000_ICR);
1479 ret_val = e1000_check_alt_mac_addr_generic(hw);
1486 * @hw: pointer to the HW structure
1490 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1492 struct e1000_mac_info *mac = &hw->mac;
1499 ret_val = mac->ops.id_led_init(hw);
1507 mac->ops.clear_vfta(hw);
1510 e1000_init_rx_addrs_generic(hw, rar_count);
1515 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1520 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1523 ret_val = mac->ops.setup_link(hw);
1526 hw->dev_spec._82575.mtu = 1500;
1534 e1000_clear_hw_cntrs_82575(hw);
1541 * @hw: pointer to the HW structure
1547 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1555 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1558 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1561 switch (hw->mac.type) {
1566 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1568 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1574 ret_val = e1000_setup_serdes_link_82575(hw);
1578 if (e1000_sgmii_active_82575(hw)) {
1582 ret_val = hw->phy.ops.reset(hw);
1588 switch (hw->phy.type) {
1591 switch (hw->phy.id) {
1598 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1601 ret_val = e1000_copper_link_setup_m88(hw);
1606 ret_val = e1000_copper_link_setup_igp(hw);
1609 ret_val = e1000_copper_link_setup_82577(hw);
1619 ret_val = e1000_setup_copper_link_generic(hw);
1626 * @hw: pointer to the HW structure
1633 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1642 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1643 !e1000_sgmii_active_82575(hw))
1652 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1655 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1657 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1659 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1663 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1666 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1669 pcs_autoneg = hw->mac.autoneg;
1683 if (hw->mac.type == e1000_82575 ||
1684 hw->mac.type == e1000_82576) {
1685 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1708 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1728 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1731 switch (hw->fc.requested_mode) {
1744 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1757 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1759 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1760 e1000_force_mac_fc_generic(hw);
1767 * @hw: pointer to the HW structure
1776 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1778 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1788 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1795 hw->phy.media_type = e1000_media_type_internal_serdes;
1798 hw->phy.media_type = e1000_media_type_copper;
1802 if (e1000_sgmii_uses_mdio_82575(hw)) {
1803 hw->phy.media_type = e1000_media_type_copper;
1811 ret_val = e1000_set_sfp_media_type_82575(hw);
1813 (hw->phy.media_type == e1000_media_type_unknown)) {
1818 hw->phy.media_type = e1000_media_type_internal_serdes;
1821 hw->phy.media_type = e1000_media_type_copper;
1835 if (hw->phy.media_type == e1000_media_type_copper)
1840 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1850 * @hw: pointer to the HW structure
1855 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1859 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1865 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1867 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1869 E1000_WRITE_FLUSH(hw);
1873 ret_val = e1000_read_sfp_data_byte(hw,
1884 ret_val = e1000_read_sfp_data_byte(hw,
1895 hw->phy.media_type = e1000_media_type_internal_serdes;
1898 hw->phy.media_type = e1000_media_type_internal_serdes;
1901 hw->phy.media_type = e1000_media_type_copper;
1903 hw->phy.media_type = e1000_media_type_unknown;
1908 hw->phy.media_type = e1000_media_type_unknown;
1913 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1919 * @hw: pointer to the HW structure
1925 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1931 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1938 switch (hw->phy.media_type) {
1954 * @hw: pointer to the HW structure
1960 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1962 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1968 * @hw: pointer to the HW structure
1973 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1977 if (hw->mac.type == e1000_82575) {
1980 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1981 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1982 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1983 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1986 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1987 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1990 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1991 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1992 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1993 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1996 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1997 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1998 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
2006 * @hw: pointer to the HW structure
2008 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2019 ret_val = e1000_check_alt_mac_addr_generic(hw);
2023 ret_val = e1000_read_mac_addr_generic(hw);
2031 * @hw: pointer to the HW structure
2036 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2042 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2047 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2048 E1000_WRITE_FLUSH(hw);
2053 * @hw: pointer to the HW structure
2058 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2060 struct e1000_phy_info *phy = &hw->phy;
2066 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2067 e1000_power_down_phy_copper(hw);
2074 * @hw: pointer to the HW structure
2078 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2082 e1000_clear_hw_cntrs_base_generic(hw);
2084 E1000_READ_REG(hw, E1000_PRC64);
2085 E1000_READ_REG(hw, E1000_PRC127);
2086 E1000_READ_REG(hw, E1000_PRC255);
2087 E1000_READ_REG(hw, E1000_PRC511);
2088 E1000_READ_REG(hw, E1000_PRC1023);
2089 E1000_READ_REG(hw, E1000_PRC1522);
2090 E1000_READ_REG(hw, E1000_PTC64);
2091 E1000_READ_REG(hw, E1000_PTC127);
2092 E1000_READ_REG(hw, E1000_PTC255);
2093 E1000_READ_REG(hw, E1000_PTC511);
2094 E1000_READ_REG(hw, E1000_PTC1023);
2095 E1000_READ_REG(hw, E1000_PTC1522);
2097 E1000_READ_REG(hw, E1000_ALGNERRC);
2098 E1000_READ_REG(hw, E1000_RXERRC);
2099 E1000_READ_REG(hw, E1000_TNCRS);
2100 E1000_READ_REG(hw, E1000_CEXTERR);
2101 E1000_READ_REG(hw, E1000_TSCTC);
2102 E1000_READ_REG(hw, E1000_TSCTFC);
2104 E1000_READ_REG(hw, E1000_MGTPRC);
2105 E1000_READ_REG(hw, E1000_MGTPDC);
2106 E1000_READ_REG(hw, E1000_MGTPTC);
2108 E1000_READ_REG(hw, E1000_IAC);
2109 E1000_READ_REG(hw, E1000_ICRXOC);
2111 E1000_READ_REG(hw, E1000_ICRXPTC);
2112 E1000_READ_REG(hw, E1000_ICRXATC);
2113 E1000_READ_REG(hw, E1000_ICTXPTC);
2114 E1000_READ_REG(hw, E1000_ICTXATC);
2115 E1000_READ_REG(hw, E1000_ICTXQEC);
2116 E1000_READ_REG(hw, E1000_ICTXQMTC);
2117 E1000_READ_REG(hw, E1000_ICRXDMTC);
2119 E1000_READ_REG(hw, E1000_CBTMPC);
2120 E1000_READ_REG(hw, E1000_HTDPMC);
2121 E1000_READ_REG(hw, E1000_CBRMPC);
2122 E1000_READ_REG(hw, E1000_RPTHC);
2123 E1000_READ_REG(hw, E1000_HGPTC);
2124 E1000_READ_REG(hw, E1000_HTCBDPC);
2125 E1000_READ_REG(hw, E1000_HGORCL);
2126 E1000_READ_REG(hw, E1000_HGORCH);
2127 E1000_READ_REG(hw, E1000_HGOTCL);
2128 E1000_READ_REG(hw, E1000_HGOTCH);
2129 E1000_READ_REG(hw, E1000_LENERRS);
2132 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2133 e1000_sgmii_active_82575(hw))
2134 E1000_READ_REG(hw, E1000_SCVPC);
2139 * @hw: pointer to the HW structure
2146 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2154 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2156 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2158 if (hw->mac.type != e1000_82575 ||
2159 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2164 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2165 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2173 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2185 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2187 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2188 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2190 rctl = E1000_READ_REG(hw, E1000_RCTL);
2194 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2195 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2196 E1000_WRITE_FLUSH(hw);
2203 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2204 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2205 E1000_WRITE_FLUSH(hw);
2207 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2208 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2211 E1000_READ_REG(hw, E1000_ROC);
2212 E1000_READ_REG(hw, E1000_RNBC);
2213 E1000_READ_REG(hw, E1000_MPC);
2218 * @hw: pointer to the HW structure
2226 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2228 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2250 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2257 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2263 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2269 * @hw: pointer to the hardware struct
2275 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2279 switch (hw->mac.type) {
2291 reg_val = E1000_READ_REG(hw, reg_offset);
2303 E1000_WRITE_REG(hw, reg_offset, reg_val);
2308 * @hw: pointer to the hardware struct
2313 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2317 switch (hw->mac.type) {
2319 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2324 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2328 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2333 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2345 * @hw: pointer to the hardware struct
2350 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2352 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2359 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2364 * @hw: pointer to the HW structure
2371 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2377 ret_val = hw->phy.ops.acquire(hw);
2381 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2383 hw->phy.ops.release(hw);
2391 * @hw: pointer to the HW structure
2397 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2403 ret_val = hw->phy.ops.acquire(hw);
2407 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2409 hw->phy.ops.release(hw);
2417 * @hw: pointer to the HW structure
2423 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2431 if (hw->mac.type != e1000_82580)
2433 if (!e1000_sgmii_active_82575(hw))
2436 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2437 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2444 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2449 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2456 * @hw: pointer to the HW structure
2461 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2467 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2471 hw->dev_spec._82575.global_device_reset = FALSE;
2473 /* 82580 does not reliably do global_device_reset due to hw errata */
2474 if (hw->mac.type == e1000_82580)
2478 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2484 ret_val = e1000_disable_pcie_master_generic(hw);
2489 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2490 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2491 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2492 E1000_WRITE_FLUSH(hw);
2497 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2501 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2507 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2509 switch (hw->device_id) {
2513 E1000_WRITE_FLUSH(hw);
2520 ret_val = e1000_get_auto_rd_done_generic(hw);
2531 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2534 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2535 E1000_READ_REG(hw, E1000_ICR);
2537 ret_val = e1000_reset_mdicnfg_82580(hw);
2542 ret_val = e1000_check_alt_mac_addr_generic(hw);
2546 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2574 * @hw: pointer to the HW structure
2580 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2589 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2610 * @hw: pointer to the HW structure
2617 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2626 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2634 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2645 * @hw: pointer to the HW structure
2651 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2660 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2674 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2686 * @hw: pointer to the HW structure
2692 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2700 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2709 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2719 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2730 * @hw: pointer to the HW structure
2736 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2746 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2758 * @hw: pointer to the HW structure
2764 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2774 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2785 * @hw: pointer to the HW structure
2790 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2797 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2802 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2804 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2811 * @hw: pointer to the HW structure
2815 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2819 return __e1000_access_emi_reg(hw, addr, data, TRUE);
2824 * @hw: pointer to the HW structure
2828 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2830 struct e1000_phy_info *phy = &hw->phy;
2840 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2844 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2848 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2856 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2864 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2872 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2877 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2881 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2886 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2891 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2896 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2900 ret_val = phy->ops.commit(hw);
2913 * @hw: pointer to the HW structure
2917 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2919 struct e1000_phy_info *phy = &hw->phy;
2929 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2933 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2937 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2941 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2945 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2949 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2953 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2957 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2961 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2966 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2970 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2975 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2980 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2985 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2990 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2995 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2999 ret_val = phy->ops.commit(hw);
3012 * @hw: pointer to the HW structure
3019 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
3025 if ((hw->mac.type < e1000_i350) ||
3026 (hw->phy.media_type != e1000_media_type_copper))
3028 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
3029 eeer = E1000_READ_REG(hw, E1000_EEER);
3032 if (!(hw->dev_spec._82575.eee_disable)) {
3033 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
3056 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
3057 E1000_WRITE_REG(hw, E1000_EEER, eeer);
3058 E1000_READ_REG(hw, E1000_IPCNFG);
3059 E1000_READ_REG(hw, E1000_EEER);
3067 * @hw: pointer to the HW structure
3074 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
3076 struct e1000_phy_info *phy = &hw->phy;
3082 if ((hw->phy.media_type != e1000_media_type_copper) ||
3087 if (!hw->dev_spec._82575.eee_disable) {
3089 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3093 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3099 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3105 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3110 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3126 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3131 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3139 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3150 * @hw: pointer to the HW structure
3156 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3158 struct e1000_phy_info *phy = &hw->phy;
3165 if ((hw->phy.media_type != e1000_media_type_copper) ||
3170 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3183 /* Due to a hw errata, if the host tries to configure the VFTA register
3190 * @hw: pointer to the HW structure
3195 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3204 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3206 E1000_WRITE_FLUSH(hw);
3212 * @hw: pointer to the HW structure
3219 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3226 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3228 E1000_WRITE_FLUSH(hw);
3234 * @hw: pointer to the HW structure
3239 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3246 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3248 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3249 E1000_WRITE_FLUSH(hw);
3251 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3255 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3256 E1000_WRITE_FLUSH(hw);
3263 * @hw: pointer to hardware structure
3271 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3286 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3292 e1000_i2c_start(hw);
3295 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3299 status = e1000_get_i2c_ack(hw);
3303 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3307 status = e1000_get_i2c_ack(hw);
3311 e1000_i2c_start(hw);
3314 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3318 status = e1000_get_i2c_ack(hw);
3322 status = e1000_clock_in_i2c_byte(hw, data);
3326 status = e1000_clock_out_i2c_bit(hw, nack);
3330 e1000_i2c_stop(hw);
3334 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3336 e1000_i2c_bus_clear(hw);
3345 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3354 * @hw: pointer to hardware structure
3362 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3374 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3380 e1000_i2c_start(hw);
3382 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3386 status = e1000_get_i2c_ack(hw);
3390 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3394 status = e1000_get_i2c_ack(hw);
3398 status = e1000_clock_out_i2c_byte(hw, data);
3402 status = e1000_get_i2c_ack(hw);
3406 e1000_i2c_stop(hw);
3410 e1000_i2c_bus_clear(hw);
3418 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3427 * @hw: pointer to hardware structure
3431 static void e1000_i2c_start(struct e1000_hw *hw)
3433 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3438 e1000_set_i2c_data(hw, &i2cctl, 1);
3439 e1000_raise_i2c_clk(hw, &i2cctl);
3444 e1000_set_i2c_data(hw, &i2cctl, 0);
3449 e1000_lower_i2c_clk(hw, &i2cctl);
3458 * @hw: pointer to hardware structure
3462 static void e1000_i2c_stop(struct e1000_hw *hw)
3464 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3469 e1000_set_i2c_data(hw, &i2cctl, 0);
3470 e1000_raise_i2c_clk(hw, &i2cctl);
3475 e1000_set_i2c_data(hw, &i2cctl, 1);
3483 * @hw: pointer to hardware structure
3488 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3497 e1000_clock_in_i2c_bit(hw, &bit);
3506 * @hw: pointer to hardware structure
3511 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3522 status = e1000_clock_out_i2c_bit(hw, bit);
3529 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3532 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3533 E1000_WRITE_FLUSH(hw);
3540 * @hw: pointer to hardware structure
3544 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3548 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3554 e1000_raise_i2c_clk(hw, &i2cctl);
3562 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3575 e1000_lower_i2c_clk(hw, &i2cctl);
3585 * @hw: pointer to hardware structure
3590 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3592 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3596 e1000_raise_i2c_clk(hw, &i2cctl);
3601 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3604 e1000_lower_i2c_clk(hw, &i2cctl);
3614 * @hw: pointer to hardware structure
3619 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3622 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3626 status = e1000_set_i2c_data(hw, &i2cctl, data);
3628 e1000_raise_i2c_clk(hw, &i2cctl);
3633 e1000_lower_i2c_clk(hw, &i2cctl);
3648 * @hw: pointer to hardware structure
3653 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3659 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3660 E1000_WRITE_FLUSH(hw);
3668 * @hw: pointer to hardware structure
3673 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3680 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3681 E1000_WRITE_FLUSH(hw);
3689 * @hw: pointer to hardware structure
3695 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3708 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3709 E1000_WRITE_FLUSH(hw);
3714 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3725 * @hw: pointer to hardware structure
3746 * @hw: pointer to hardware structure
3751 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3753 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3758 e1000_i2c_start(hw);
3760 e1000_set_i2c_data(hw, &i2cctl, 1);
3763 e1000_raise_i2c_clk(hw, &i2cctl);
3768 e1000_lower_i2c_clk(hw, &i2cctl);
3774 e1000_i2c_start(hw);
3777 e1000_i2c_stop(hw);