dev/e1000/e1000_82542.c

41 static s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
42 static s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
43 static s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
44 static s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
45 static s32  e1000_reset_hw_82542(struct e1000_hw *hw);
46 static s32  e1000_init_hw_82542(struct e1000_hw *hw);
47 static s32  e1000_setup_link_82542(struct e1000_hw *hw);
48 static s32  e1000_led_on_82542(struct e1000_hw *hw);
49 static s32  e1000_led_off_82542(struct e1000_hw *hw);
50 static int  e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
51 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
52 static s32  e1000_read_mac_addr_82542(struct e1000_hw *hw);
56  *  @hw: pointer to the HW structure
58 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
60 	struct e1000_phy_info *phy = &hw->phy;
72  *  @hw: pointer to the HW structure
74 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
76 	struct e1000_nvm_info *nvm = &hw->nvm;
98  *  @hw: pointer to the HW structure
100 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
102 	struct e1000_mac_info *mac = &hw->mac;
107 	hw->phy.media_type = e1000_media_type_fiber;
122 	/* hw initialization */
155  *  @hw: pointer to the HW structure
159 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
163 	hw->mac.ops.init_params = e1000_init_mac_params_82542;
164 	hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
165 	hw->phy.ops.init_params = e1000_init_phy_params_82542;
170  *  @hw: pointer to the HW structure
173  *  adapter is attached and stores it in the hw structure.
175 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
179 	hw->bus.type = e1000_bus_type_pci;
180 	hw->bus.speed = e1000_bus_speed_unknown;
181 	hw->bus.width = e1000_bus_width_unknown;
188  *  @hw: pointer to the HW structure
192 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
194 	struct e1000_bus_info *bus = &hw->bus;
200 	if (hw->revision_id == E1000_REVISION_2) {
202 		e1000_pci_clear_mwi(hw);
206 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
208 	E1000_WRITE_REG(hw, E1000_RCTL, 0);
209 	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
210 	E1000_WRITE_FLUSH(hw);
218 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
221 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
223 	hw->nvm.ops.reload(hw);
226 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
227 	E1000_READ_REG(hw, E1000_ICR);
229 	if (hw->revision_id == E1000_REVISION_2) {
231 			e1000_pci_set_mwi(hw);
239  *  @hw: pointer to the HW structure
243 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
245 	struct e1000_mac_info *mac = &hw->mac;
246 	struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
254 	E1000_WRITE_REG(hw, E1000_VET, 0);
255 	mac->ops.clear_vfta(hw);
258 	if (hw->revision_id == E1000_REVISION_2) {
260 		e1000_pci_clear_mwi(hw);
261 		E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
262 		E1000_WRITE_FLUSH(hw);
267 	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
270 	if (hw->revision_id == E1000_REVISION_2) {
271 		E1000_WRITE_REG(hw, E1000_RCTL, 0);
272 		E1000_WRITE_FLUSH(hw);
274 		if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
275 			e1000_pci_set_mwi(hw);
281 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
289 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
290 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
294 	ret_val = e1000_setup_link_82542(hw);
302 	e1000_clear_hw_cntrs_82542(hw);
309  *  @hw: pointer to the HW structure
317 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
319 	struct e1000_mac_info *mac = &hw->mac;
324 	ret_val = e1000_set_default_fc_generic(hw);
328 	hw->fc.requested_mode &= ~e1000_fc_tx_pause;
331 		hw->fc.requested_mode &= ~e1000_fc_rx_pause;
337 	hw->fc.current_mode = hw->fc.requested_mode;
340 		  hw->fc.current_mode);
343 	ret_val = mac->ops.setup_physical_interface(hw);
355 	E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
356 	E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
357 	E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
359 	E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
361 	ret_val = e1000_set_fc_watermarks_generic(hw);
369  *  @hw: pointer to the HW structure
373 static s32 e1000_led_on_82542(struct e1000_hw *hw)
375 	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
381 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
388  *  @hw: pointer to the HW structure
392 static s32 e1000_led_off_82542(struct e1000_hw *hw)
394 	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
400 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
407  *  @hw: pointer to the HW structure
414 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
433 	E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
434 	E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
538  *  @hw: pointer to the HW structure
542 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
546 	e1000_clear_hw_cntrs_base_generic(hw);
548 	E1000_READ_REG(hw, E1000_PRC64);
549 	E1000_READ_REG(hw, E1000_PRC127);
550 	E1000_READ_REG(hw, E1000_PRC255);
551 	E1000_READ_REG(hw, E1000_PRC511);
552 	E1000_READ_REG(hw, E1000_PRC1023);
553 	E1000_READ_REG(hw, E1000_PRC1522);
554 	E1000_READ_REG(hw, E1000_PTC64);
555 	E1000_READ_REG(hw, E1000_PTC127);
556 	E1000_READ_REG(hw, E1000_PTC255);
557 	E1000_READ_REG(hw, E1000_PTC511);
558 	E1000_READ_REG(hw, E1000_PTC1023);
559 	E1000_READ_REG(hw, E1000_PTC1522);
564  *  @hw: pointer to the HW structure
568 s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
577 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
582 		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
583 		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
587 		hw->mac.addr[i] = hw->mac.perm_addr[i];