dev/e1000/e1000_82541.c

130 	struct e1000_nvm_info *nvm = &hw->nvm;
137 	switch (nvm->override) {
139 		nvm->type = e1000_nvm_eeprom_spi;
143 		nvm->type = e1000_nvm_eeprom_spi;
147 		nvm->type = e1000_nvm_eeprom_microwire;
151 		nvm->type = e1000_nvm_eeprom_microwire;
155 		nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi
160 	if (nvm->type == e1000_nvm_eeprom_spi) {
161 		nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;
162 		nvm->delay_usec = 1;
163 		nvm->opcode_bits = 8;
164 		nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;
167 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
168 		nvm->ops.read		= e1000_read_nvm_spi;
169 		nvm->ops.release	= e1000_release_nvm_generic;
170 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
171 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
172 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
173 		nvm->ops.write		= e1000_write_nvm_spi;
176 		 * nvm->word_size must be discovered after the pointers
177 		 * are set so we can verify the size from the nvm image
181 		nvm->word_size = 64;
182 		ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
193 			nvm->word_size = 1 << size;
196 		nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;
197 		nvm->delay_usec = 50;
198 		nvm->opcode_bits = 3;
199 		nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;
202 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
203 		nvm->ops.read		= e1000_read_nvm_microwire;
204 		nvm->ops.release	= e1000_release_nvm_generic;
205 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
206 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
207 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
208 		nvm->ops.write		= e1000_write_nvm_microwire;
286 	hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
1289 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);