Lines Matching refs:hw
41 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
42 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
44 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
48 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
51 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
53 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
54 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
55 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
58 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
59 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
62 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
63 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
64 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
66 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
68 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
70 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
71 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
72 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
73 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
87 * @hw: pointer to the HW structure
89 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
91 struct e1000_phy_info *phy = &hw->phy;
96 if (hw->phy.media_type != e1000_media_type_copper) {
127 ret_val = e1000_get_phy_id(hw);
138 * @hw: pointer to the HW structure
140 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
142 struct e1000_nvm_info *nvm = &hw->nvm;
143 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
194 * @hw: pointer to the HW structure
196 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
198 struct e1000_mac_info *mac = &hw->mac;
203 switch (hw->device_id) {
205 hw->phy.media_type = e1000_media_type_internal_serdes;
211 hw->phy.media_type = e1000_media_type_copper;
227 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
238 /* hw initialization */
269 hw->mac.ops.set_lan_id(hw);
276 * @hw: pointer to the HW structure
280 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
284 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
285 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
286 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
291 * @hw: pointer to the HW structure
295 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
301 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
302 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
307 * @hw: pointer to the HW structure
311 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
317 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
318 e1000_release_swfw_sync_80003es2lan(hw, mask);
323 * @hw: pointer to the HW structure
328 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
336 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
341 * @hw: pointer to the HW structure
345 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
353 e1000_release_swfw_sync_80003es2lan(hw, mask);
358 * @hw: pointer to the HW structure
362 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
368 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
372 ret_val = e1000_acquire_nvm_generic(hw);
375 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
382 * @hw: pointer to the HW structure
386 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
390 e1000_release_nvm_generic(hw);
391 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
396 * @hw: pointer to the HW structure
402 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
413 if (e1000_get_hw_semaphore_generic(hw))
416 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
423 e1000_put_hw_semaphore_generic(hw);
434 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
436 e1000_put_hw_semaphore_generic(hw);
443 * @hw: pointer to the HW structure
449 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
458 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
460 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
462 e1000_put_hw_semaphore_generic(hw);
467 * @hw: pointer to the HW structure
473 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
482 ret_val = e1000_acquire_phy_80003es2lan(hw);
497 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
499 e1000_release_phy_80003es2lan(hw);
503 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
511 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
514 e1000_release_phy_80003es2lan(hw);
520 ret_val = e1000_read_phy_reg_mdic(hw,
526 ret_val = e1000_read_phy_reg_mdic(hw,
531 e1000_release_phy_80003es2lan(hw);
538 * @hw: pointer to the HW structure
544 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
553 ret_val = e1000_acquire_phy_80003es2lan(hw);
568 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
570 e1000_release_phy_80003es2lan(hw);
574 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
582 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
585 e1000_release_phy_80003es2lan(hw);
591 ret_val = e1000_write_phy_reg_mdic(hw,
597 ret_val = e1000_write_phy_reg_mdic(hw,
602 e1000_release_phy_80003es2lan(hw);
609 * @hw: pointer to the HW structure
616 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
621 return e1000_write_nvm_spi(hw, offset, words, data);
626 * @hw: pointer to the HW structure
631 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
638 if (hw->bus.func == 1)
642 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
657 * @hw: pointer to the HW structure
662 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
670 if (!(hw->phy.ops.read_reg))
676 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
687 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
691 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
702 if (hw->phy.autoneg_wait_to_complete) {
705 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
714 ret_val = e1000_phy_reset_dsp_generic(hw);
720 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
726 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
735 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
752 * @hw: pointer to the HW structure
757 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
759 struct e1000_phy_info *phy = &hw->phy;
765 if (!(hw->phy.ops.read_reg))
768 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
787 * @hw: pointer to the HW structure
793 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
800 if (hw->phy.media_type == e1000_media_type_copper) {
801 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
803 hw->phy.ops.cfg_on_link_up(hw);
805 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
815 * @hw: pointer to the HW structure
819 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
830 ret_val = e1000_disable_pcie_master_generic(hw);
835 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
837 E1000_WRITE_REG(hw, E1000_RCTL, 0);
838 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
839 E1000_WRITE_FLUSH(hw);
843 ctrl = E1000_READ_REG(hw, E1000_CTRL);
845 ret_val = e1000_acquire_phy_80003es2lan(hw);
850 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
851 e1000_release_phy_80003es2lan(hw);
854 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
858 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
866 ret_val = e1000_get_auto_rd_done_generic(hw);
872 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
873 E1000_READ_REG(hw, E1000_ICR);
875 return e1000_check_alt_mac_addr_generic(hw);
880 * @hw: pointer to the HW structure
882 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
884 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
886 struct e1000_mac_info *mac = &hw->mac;
894 e1000_initialize_hw_bits_80003es2lan(hw);
897 ret_val = mac->ops.id_led_init(hw);
904 mac->ops.clear_vfta(hw);
907 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
912 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
915 ret_val = mac->ops.setup_link(hw);
921 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
925 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
934 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
937 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
940 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
943 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
946 reg_data = E1000_READ_REG(hw, E1000_TCTL);
948 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
951 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
954 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
957 reg_data = E1000_READ_REG(hw, E1000_TIPG);
960 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
962 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
964 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
967 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
970 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
975 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
983 e1000_clear_hw_cntrs_80003es2lan(hw);
989 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
990 * @hw: pointer to the HW structure
994 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
1001 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1003 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1006 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1008 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1011 reg = E1000_READ_REG(hw, E1000_TARC(0));
1013 if (hw->phy.media_type != e1000_media_type_copper)
1015 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1018 reg = E1000_READ_REG(hw, E1000_TARC(1));
1019 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1023 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1028 reg = E1000_READ_REG(hw, E1000_RFCTL);
1030 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1037 * @hw: pointer to the HW structure
1041 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1043 struct e1000_phy_info *phy = &hw->phy;
1050 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1069 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1098 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1103 ret_val = hw->phy.ops.commit(hw);
1113 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1118 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1122 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1126 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1135 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1137 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1139 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1147 if (!hw->mac.ops.check_mng_mode(hw)) {
1150 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1155 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1161 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1170 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1175 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1184 * @hw: pointer to the HW structure
1189 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1197 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1200 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1206 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1210 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1215 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1220 e1000_read_kmrn_reg_80003es2lan(hw,
1227 e1000_write_kmrn_reg_80003es2lan(hw,
1233 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1237 return e1000_setup_copper_link_generic(hw);
1242 * @hw: pointer to the HW structure
1248 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1256 if (hw->phy.media_type == e1000_media_type_copper) {
1257 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1263 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1265 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1273 * @hw: pointer to the HW structure
1279 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1290 e1000_write_kmrn_reg_80003es2lan(hw,
1297 tipg = E1000_READ_REG(hw, E1000_TIPG);
1300 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1303 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1308 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1320 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1325 * @hw: pointer to the HW structure
1330 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1341 e1000_write_kmrn_reg_80003es2lan(hw,
1348 tipg = E1000_READ_REG(hw, E1000_TIPG);
1351 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1354 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1359 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1368 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1373 * @hw: pointer to the HW structure
1381 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1389 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1395 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1396 E1000_WRITE_FLUSH(hw);
1400 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1403 e1000_release_mac_csr_80003es2lan(hw);
1410 * @hw: pointer to the HW structure
1418 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1426 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1432 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1433 E1000_WRITE_FLUSH(hw);
1437 e1000_release_mac_csr_80003es2lan(hw);
1444 * @hw: pointer to the HW structure
1446 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1456 ret_val = e1000_check_alt_mac_addr_generic(hw);
1460 return e1000_read_mac_addr_generic(hw);
1465 * @hw: pointer to the HW structure
1470 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1473 if (!(hw->mac.ops.check_mng_mode(hw) ||
1474 hw->phy.ops.check_reset_block(hw)))
1475 e1000_power_down_phy_copper(hw);
1482 * @hw: pointer to the HW structure
1486 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1490 e1000_clear_hw_cntrs_base_generic(hw);
1492 E1000_READ_REG(hw, E1000_PRC64);
1493 E1000_READ_REG(hw, E1000_PRC127);
1494 E1000_READ_REG(hw, E1000_PRC255);
1495 E1000_READ_REG(hw, E1000_PRC511);
1496 E1000_READ_REG(hw, E1000_PRC1023);
1497 E1000_READ_REG(hw, E1000_PRC1522);
1498 E1000_READ_REG(hw, E1000_PTC64);
1499 E1000_READ_REG(hw, E1000_PTC127);
1500 E1000_READ_REG(hw, E1000_PTC255);
1501 E1000_READ_REG(hw, E1000_PTC511);
1502 E1000_READ_REG(hw, E1000_PTC1023);
1503 E1000_READ_REG(hw, E1000_PTC1522);
1505 E1000_READ_REG(hw, E1000_ALGNERRC);
1506 E1000_READ_REG(hw, E1000_RXERRC);
1507 E1000_READ_REG(hw, E1000_TNCRS);
1508 E1000_READ_REG(hw, E1000_CEXTERR);
1509 E1000_READ_REG(hw, E1000_TSCTC);
1510 E1000_READ_REG(hw, E1000_TSCTFC);
1512 E1000_READ_REG(hw, E1000_MGTPRC);
1513 E1000_READ_REG(hw, E1000_MGTPDC);
1514 E1000_READ_REG(hw, E1000_MGTPTC);
1516 E1000_READ_REG(hw, E1000_IAC);
1517 E1000_READ_REG(hw, E1000_ICRXOC);
1519 E1000_READ_REG(hw, E1000_ICRXPTC);
1520 E1000_READ_REG(hw, E1000_ICRXATC);
1521 E1000_READ_REG(hw, E1000_ICTXPTC);
1522 E1000_READ_REG(hw, E1000_ICTXATC);
1523 E1000_READ_REG(hw, E1000_ICTXQEC);
1524 E1000_READ_REG(hw, E1000_ICTXQMTC);
1525 E1000_READ_REG(hw, E1000_ICRXDMTC);