drm2/radeon/si.c

548 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
556 	yclk.full = dfixed_const(wm->yclk);
558 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
568 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
576 	yclk.full = dfixed_const(wm->yclk);
578 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
588 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
596 	sclk.full = dfixed_const(wm->sclk);
608 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
613 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
622 	disp_clk.full = dfixed_const(wm->disp_clk);
624 	a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
628 	sclk.full = dfixed_const(wm->sclk);
630 	a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
645 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
648 	u32 dram_bandwidth = dce6_dram_bandwidth(wm);
649 	u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
650 	u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
655 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
668 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
670 	bpp.full = dfixed_const(wm->bytes_per_pixel);
671 	src_width.full = dfixed_const(wm->src_width);
673 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
679 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
683 	u32 available_bandwidth = dce6_available_bandwidth(wm);
686 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
687 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
688 		(wm->num_heads * cursor_line_pair_return_time);
694 	if (wm->num_heads == 0)
699 	if ((wm->vsc.full > a.full) ||
700 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
701 	    (wm->vtaps >= 5) ||
702 	    ((wm->vsc.full >= a.full) && wm->interlaced))
708 	b.full = dfixed_const(wm->num_heads);
712 	c.full = dfixed_const(wm->disp_clk);
721 	c.full = dfixed_const(wm->disp_clk);
723 	c.full = dfixed_const(wm->bytes_per_pixel);
728 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
735 	if (line_fill_time < wm->active_time)
738 		return latency + (line_fill_time - wm->active_time);
742 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
744 	if (dce6_average_bandwidth(wm) <=
745 	    (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
751 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
753 	if (dce6_average_bandwidth(wm) <=
754 	    (dce6_available_bandwidth(wm) / wm->num_heads))
760 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
762 	u32 lb_partitions = wm->lb_size / wm->src_width;
763 	u32 line_time = wm->active_time + wm->blank_time;
769 	if (wm->vsc.full > a.full)
772 		if (lb_partitions <= (wm->vtaps + 1))
778 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
780 	if (dce6_latency_watermark(wm) <= latency_hiding)
791 	struct dce6_wm_params wm;
807 		wm.yclk = rdev->pm.current_mclk * 10;
808 		wm.sclk = rdev->pm.current_sclk * 10;
809 		wm.disp_clk = mode->clock;
810 		wm.src_width = mode->crtc_hdisplay;
811 		wm.active_time = mode->crtc_hdisplay * pixel_period;
812 		wm.blank_time = line_time - wm.active_time;
813 		wm.interlaced = false;
815 			wm.interlaced = true;
816 		wm.vsc = radeon_crtc->vsc;
817 		wm.vtaps = 1;
819 			wm.vtaps = 2;
820 		wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
821 		wm.lb_size = lb_size;
823 			wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
825 			wm.dram_channels = si_get_number_of_dram_channels(rdev);
826 		wm.num_heads = num_heads;
829 		latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
831 		/* wm.yclk = low clk; wm.sclk = low clk */
832 		latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
836 		if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
837 		    !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
838 		    !dce6_check_latency_hiding(&wm) ||
870 	/* select wm A */
879 	/* select wm B */