drm2/radeon/radeon_legacy_tv.c

243 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
256 	if (tv_dac->tv_std == TV_STD_NTSC ||
257 	    tv_dac->tv_std == TV_STD_NTSC_J ||
258 	    tv_dac->tv_std == TV_STD_PAL_M) {
391 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
396 	WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
397 	h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
398 	v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
401 		tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
403 		if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
407 		tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
409 		if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
418 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
419 	WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
420 	WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
421 	WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
429 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
452 	if (tv_dac->tv_std == TV_STD_NTSC ||
453 	    tv_dac->tv_std == TV_STD_NTSC_J ||
454 	    tv_dac->tv_std == TV_STD_PAL_M ||
455 	    tv_dac->tv_std == TV_STD_PAL_60)
461 	h_offset = tv_dac->h_pos * H_POS_UNIT;
463 	if (tv_dac->tv_std == TV_STD_NTSC ||
464 	    tv_dac->tv_std == TV_STD_NTSC_J ||
465 	    tv_dac->tv_std == TV_STD_PAL_M) {
477 	h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
478 		     p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
480 	tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
481 	tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
492 	if (tv_dac->tv_std == TV_STD_NTSC ||
493 	    tv_dac->tv_std == TV_STD_NTSC_J ||
494 	    tv_dac->tv_std == TV_STD_PAL_M ||
495 	    tv_dac->tv_std == TV_STD_PAL_60)
496 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
498 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
503 		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
505 	tv_dac->tv.hrestart = restart % h_total;
507 	tv_dac->tv.vrestart = restart % v_total;
509 	tv_dac->tv.frestart = restart % f_total;
512 		  (unsigned)tv_dac->tv.frestart,
513 		  (unsigned)tv_dac->tv.vrestart,
514 		  (unsigned)tv_dac->tv.hrestart);
517 	if (tv_dac->tv_std == TV_STD_NTSC ||
518 	    tv_dac->tv_std == TV_STD_NTSC_J ||
519 	    tv_dac->tv_std == TV_STD_PAL_M)
521 			      (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
524 			      (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
526 	tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
529 	DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
541 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
570 	if (tv_dac->tv_std == TV_STD_NTSC ||
571 	    tv_dac->tv_std == TV_STD_NTSC_J)
580 	if (tv_dac->tv_std == TV_STD_NTSC ||
581 	    tv_dac->tv_std == TV_STD_NTSC_J) {
586 	} else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
615 	if (tv_dac->tv_std == TV_STD_NTSC ||
616 	    tv_dac->tv_std == TV_STD_NTSC_J ||
617 	    tv_dac->tv_std == TV_STD_PAL_M ||
618 	    tv_dac->tv_std == TV_STD_PAL_60)
638 	if (tv_dac->tv_std == TV_STD_NTSC ||
639 	    tv_dac->tv_std == TV_STD_NTSC_J ||
640 	    tv_dac->tv_std == TV_STD_PAL_M ||
641 	    tv_dac->tv_std == TV_STD_PAL_60) {
675 	tv_dac->tv.timing_cntl = tmp;
677 	if (tv_dac->tv_std == TV_STD_NTSC ||
678 	    tv_dac->tv_std == TV_STD_NTSC_J ||
679 	    tv_dac->tv_std == TV_STD_PAL_M ||
680 	    tv_dac->tv_std == TV_STD_PAL_60)
681 		tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
683 		tv_dac_cntl = tv_dac->pal_tvdac_adj;
687 	if (tv_dac->tv_std == TV_STD_NTSC ||
688 	    tv_dac->tv_std == TV_STD_NTSC_J)
693 	if (tv_dac->tv_std == TV_STD_NTSC ||
694 	    tv_dac->tv_std == TV_STD_NTSC_J) {
728 	tv_dac->tv.tv_uv_adr = 0xc8;
730 	if (tv_dac->tv_std == TV_STD_NTSC ||
731 	    tv_dac->tv_std == TV_STD_NTSC_J ||
732 	    tv_dac->tv_std == TV_STD_PAL_M ||
733 	    tv_dac->tv_std == TV_STD_PAL_60) {
744 		if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
749 		if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
819 	WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);