Lines Matching refs:lvds_gen_cntl
52 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
58 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
59 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
98 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
100 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
104 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
106 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
113 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
115 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
116 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
117 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
119 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
120 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
123 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
185 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
199 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
203 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
204 lvds_gen_cntl = lvds->lvds_gen_cntl;
210 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
212 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
213 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
226 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
231 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
234 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);