Lines Matching defs:fp_gen_cntl
730 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
735 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
740 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
744 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
784 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
830 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
834 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
836 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
845 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
847 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
851 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
853 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
855 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
857 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
860 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
861 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
863 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
868 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);