drm2/radeon/radeon_clocks.c

109 	struct radeon_pll *p1pll = &rdev->clock.p1pll;
121 	p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
122 	p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
123 	if (p1pll->reference_div < 2)
124 		p1pll->reference_div = 12;
125 	p2pll->reference_div = p1pll->reference_div;
129 		p1pll->pll_in_min = 100;
130 		p1pll->pll_in_max = 1350;
131 		p1pll->pll_out_min = 20000;
132 		p1pll->pll_out_max = 50000;
138 		p1pll->pll_in_min = 40;
139 		p1pll->pll_in_max = 500;
140 		p1pll->pll_out_min = 12500;
141 		p1pll->pll_out_max = 35000;
150 	spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
183 	struct radeon_pll *p1pll = &rdev->clock.p1pll;
198 		if (p1pll->reference_div < 2) {
202 					p1pll->reference_div =
205 					p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
206 				if (p1pll->reference_div < 2)
207 					p1pll->reference_div = 12;
209 				p1pll->reference_div = 12;
231 				p1pll->reference_freq = 1432;
236 				p1pll->reference_freq = 2700;
241 			p1pll->reference_div =
243 			if (p1pll->reference_div < 2)
244 				p1pll->reference_div = 12;
245 			p2pll->reference_div = p1pll->reference_div;
248 				p1pll->pll_in_min = 100;
249 				p1pll->pll_in_max = 1350;
250 				p1pll->pll_out_min = 20000;
251 				p1pll->pll_out_max = 50000;
257 				p1pll->pll_in_min = 40;
258 				p1pll->pll_in_max = 500;
259 				p1pll->pll_out_min = 12500;
260 				p1pll->pll_out_max = 35000;
280 		p1pll->min_post_div = 2;
281 		p1pll->max_post_div = 0x7f;
282 		p1pll->min_frac_feedback_div = 0;
283 		p1pll->max_frac_feedback_div = 9;
289 		p1pll->min_post_div = 1;
290 		p1pll->max_post_div = 16;
291 		p1pll->min_frac_feedback_div = 0;
292 		p1pll->max_frac_feedback_div = 0;
310 	p1pll->min_ref_div = 2;
311 	p1pll->max_ref_div = 0x3ff;
312 	p1pll->min_feedback_div = 4;
313 	p1pll->max_feedback_div = 0x7ff;
314 	p1pll->best_vco = 0;