drm2/radeon/radeon_clocks.c

40 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
42 	struct radeon_pll *spll = &rdev->clock.spll;
70 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
72 	struct radeon_pll *mpll = &rdev->clock.mpll;
106 	struct radeon_device *rdev = dev->dev_private;
107 	struct device_node *dp = rdev->pdev->dev.of_node;
109 	struct radeon_pll *p1pll = &rdev->clock.p1pll;
110 	struct radeon_pll *p2pll = &rdev->clock.p2pll;
111 	struct radeon_pll *spll = &rdev->clock.spll;
112 	struct radeon_pll *mpll = &rdev->clock.mpll;
128 	if (rdev->family >= CHIP_R420) {
148 	rdev->clock.max_pixel_clock = 35000;
157 		rdev->clock.default_sclk = (*val) / 10;
159 		rdev->clock.default_sclk =
160 			radeon_legacy_get_engine_clock(rdev);
164 		rdev->clock.default_mclk = (*val) / 10;
166 		rdev->clock.default_mclk =
167 			radeon_legacy_get_memory_clock(rdev);
182 	struct radeon_device *rdev = dev->dev_private;
183 	struct radeon_pll *p1pll = &rdev->clock.p1pll;
184 	struct radeon_pll *p2pll = &rdev->clock.p2pll;
185 	struct radeon_pll *dcpll = &rdev->clock.dcpll;
186 	struct radeon_pll *spll = &rdev->clock.spll;
187 	struct radeon_pll *mpll = &rdev->clock.mpll;
190 	if (rdev->is_atom_bios)
199 			if (!ASIC_IS_AVIVO(rdev)) {
201 				if (ASIC_IS_R300(rdev))
213 		if (rdev->family < CHIP_RS600) {
222 		if (ASIC_IS_AVIVO(rdev)) {
228 			rdev->clock.max_pixel_clock = 35000;
230 			if (rdev->flags & RADEON_IS_IGP) {
247 			if (rdev->family >= CHIP_R420) {
271 			rdev->clock.default_sclk =
272 			    radeon_legacy_get_engine_clock(rdev);
273 			rdev->clock.default_mclk =
274 			    radeon_legacy_get_memory_clock(rdev);
279 	if (ASIC_IS_AVIVO(rdev)) {
340 	if (!rdev->clock.default_sclk)
341 		rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
342 	if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
343 		rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
345 	rdev->pm.current_sclk = rdev->clock.default_sclk;
346 	rdev->pm.current_mclk = rdev->clock.default_mclk;
351 static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
355 	struct radeon_pll *spll = &rdev->clock.spll;
390 void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
398 	eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
476 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
481 		if (rdev->flags & RADEON_SINGLE_CRTC) {
497 		} else if (ASIC_IS_R300(rdev)) {
498 			if ((rdev->family == CHIP_RS400) ||
499 			    (rdev->family == CHIP_RS480)) {
546 			} else if (rdev->family >= CHIP_RV350) {
621 					if (rdev->mc.vram_width == 64) {
674 			if (((rdev->family == CHIP_RV250) &&
678 			    || ((rdev->family == CHIP_RV100)
689 			if ((rdev->family == CHIP_RV200) ||
690 			    (rdev->family == CHIP_RV250) ||
691 			    (rdev->family == CHIP_RV280)) {
696 				if (((rdev->family == CHIP_RV200) ||
697 				     (rdev->family == CHIP_RV250)) &&
708 			if (((rdev->family == CHIP_RV200) ||
709 			     (rdev->family == CHIP_RV250)) &&
741 		if (rdev->flags & RADEON_SINGLE_CRTC) {
751 		} else if ((rdev->family == CHIP_RS400) ||
752 			   (rdev->family == CHIP_RS480)) {
790 		} else if (rdev->family >= CHIP_RV350) {
846 			if (rdev->flags & RADEON_SINGLE_CRTC) {
858 			} else if ((rdev->family == CHIP_R300) ||
859 				   (rdev->family == CHIP_R350)) {
871 			if ((rdev->family == CHIP_R300) ||
872 			    (rdev->family == CHIP_R350)) {
881 			if (rdev->flags & RADEON_IS_IGP) {
889 			if ((rdev->family == CHIP_RV200) ||
890 			    (rdev->family == CHIP_RV250) ||
891 			    (rdev->family == CHIP_RV280)) {