drm2/radeon/r600_cs.c

373 	size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
453 	if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
465 				 radeon_bo_size(track->cb_color_bo[i]),
492 			    radeon_bo_size(track->cb_color_frag_bo[i])) {
497 					 radeon_bo_size(track->cb_color_frag_bo[i]));
510 		    radeon_bo_size(track->cb_color_tile_bo[i])) {
515 				 radeon_bo_size(track->cb_color_tile_bo[i]));
567 		tmp = radeon_bo_size(track->db_bo) - track->db_offset;
572 					radeon_bo_size(track->db_bo));
577 		size = radeon_bo_size(track->db_bo);
633 		if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
637 					radeon_bo_size(track->db_bo));
704 		if (size > radeon_bo_size(track->htile_bo)) {
706 				 __func__, __LINE__, radeon_bo_size(track->htile_bo),
733 					if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
736 							  radeon_bo_size(track->vgt_strmout_bo[i]));
1677 	if ((l0_size + word2) > radeon_bo_size(texture)) {
1681 			 l0_size, radeon_bo_size(texture));
1686 	if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1688 		  w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1888 			if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1890 					 (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
1918 			if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1920 					 (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
2082 				if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2085 						 size + offset, radeon_bo_size(reloc->robj));
2086 					ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2194 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2196 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2227 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2229 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2246 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2248 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2275 		if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2277 				  (uintmax_t)offset + 8, radeon_bo_size(reloc->robj));
2300 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2302 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2324 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2326 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2502 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2504 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2569 			if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2571 					 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2574 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2576 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2592 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2594 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));