Lines Matching refs:dst_offset
2466 u64 src_offset, dst_offset;
2489 dst_offset = radeon_get_ib_value(p, idx+1);
2490 dst_offset <<= 8;
2495 dst_offset = radeon_get_ib_value(p, idx+1);
2496 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2502 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2504 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2528 dst_offset = radeon_get_ib_value(p, idx+5);
2529 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2539 dst_offset = radeon_get_ib_value(p, idx+1);
2540 dst_offset <<= 8;
2548 dst_offset = radeon_get_ib_value(p, idx+1);
2549 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2559 dst_offset = radeon_get_ib_value(p, idx+1);
2560 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
2574 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2576 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2590 dst_offset = radeon_get_ib_value(p, idx+1);
2591 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
2592 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2594 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));