drm2/radeon/r600_cs.c

1127 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1168 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1170 		track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1189 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1226 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1229 			} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1298 			ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1329 			ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1365 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1368 		track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1379 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1381 		track->db_bo_mc = reloc->lobj.gpu_offset;
1392 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1461 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1470 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1756 		offset = reloc->lobj.gpu_offset +
1797 		offset = reloc->lobj.gpu_offset +
1849 			offset = reloc->lobj.gpu_offset +
1886 			offset = reloc->lobj.gpu_offset + tmp;
1916 			offset = reloc->lobj.gpu_offset + tmp;
1942 			ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1958 			offset = reloc->lobj.gpu_offset +
1980 		offset = reloc->lobj.gpu_offset +
2045 				base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2047 					if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2049 					else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2059 				mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2065 								reloc->lobj.tiling_flags);
2089 				offset64 = reloc->lobj.gpu_offset + offset;
2199 			ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2232 			offset += reloc->lobj.gpu_offset;
2251 			offset += reloc->lobj.gpu_offset;
2280 		offset += reloc->lobj.gpu_offset;
2305 			offset += reloc->lobj.gpu_offset;
2329 			offset += reloc->lobj.gpu_offset;
2492 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2498 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2499 				ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2526 					ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2530 					ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2531 					ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2536 					ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2537 					ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2541 					ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2551 					ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2552 					ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2553 					ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2554 					ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2562 					ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2563 					ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2564 					ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2565 					ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
2597 			ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2598 			ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;