drm2/radeon/r600_blit_kms.c

76 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
90 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
91 	radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
92 	radeon_ring_write(ring, gpu_addr >> 8);
95 		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
96 		radeon_ring_write(ring, 2 << 0);
99 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
100 	radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
101 	radeon_ring_write(ring, (pitch << 0) | (slice << 10));
103 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
104 	radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
105 	radeon_ring_write(ring, 0);
107 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
108 	radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
109 	radeon_ring_write(ring, cb_color_info);
111 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
112 	radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
113 	radeon_ring_write(ring, 0);
115 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
116 	radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
117 	radeon_ring_write(ring, 0);
119 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
120 	radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
121 	radeon_ring_write(ring, 0);
130 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
138 	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
139 	radeon_ring_write(ring, sync_type);
140 	radeon_ring_write(ring, cp_coher_size);
141 	radeon_ring_write(ring, mc_addr >> 8);
142 	radeon_ring_write(ring, 10); /* poll interval */
149 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
158 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
159 	radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
160 	radeon_ring_write(ring, gpu_addr >> 8);
162 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
163 	radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
164 	radeon_ring_write(ring, sq_pgm_resources);
166 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
167 	radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
168 	radeon_ring_write(ring, 0);
172 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
173 	radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
174 	radeon_ring_write(ring, gpu_addr >> 8);
176 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
177 	radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
178 	radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
180 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
181 	radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
182 	radeon_ring_write(ring, 2);
184 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
185 	radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
186 	radeon_ring_write(ring, 0);
196 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
205 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
206 	radeon_ring_write(ring, 0x460);
207 	radeon_ring_write(ring, gpu_addr & 0xffffffff);
208 	radeon_ring_write(ring, 48 - 1);
209 	radeon_ring_write(ring, sq_vtx_constant_word2);
210 	radeon_ring_write(ring, 1 << 0);
211 	radeon_ring_write(ring, 0);
212 	radeon_ring_write(ring, 0);
213 	radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
233 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
256 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
257 	radeon_ring_write(ring, 0);
258 	radeon_ring_write(ring, sq_tex_resource_word0);
259 	radeon_ring_write(ring, sq_tex_resource_word1);
260 	radeon_ring_write(ring, gpu_addr >> 8);
261 	radeon_ring_write(ring, gpu_addr >> 8);
262 	radeon_ring_write(ring, sq_tex_resource_word4);
263 	radeon_ring_write(ring, 0);
264 	radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
272 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
273 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
274 	radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
275 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
276 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
278 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
279 	radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
280 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
281 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
283 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
284 	radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
285 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
286 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
293 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
294 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
295 	radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
296 	radeon_ring_write(ring, DI_PT_RECTLIST);
298 	radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
299 	radeon_ring_write(ring,
305 	radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
306 	radeon_ring_write(ring, 1);
308 	radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
309 	radeon_ring_write(ring, 3);
310 	radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
318 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
474 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
475 	radeon_ring_write(ring,
480 	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
481 	radeon_ring_write(ring, dwords);
484 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
485 	radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
486 	radeon_ring_write(ring, sq_config);
487 	radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
488 	radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
489 	radeon_ring_write(ring, sq_thread_resource_mgmt);
490 	radeon_ring_write(ring, sq_stack_resource_mgmt_1);
491 	radeon_ring_write(ring, sq_stack_resource_mgmt_2);
669 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
699 	r = radeon_ring_lock(rdev, ring, ring_size);
707 		radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
722 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
727 		radeon_ring_unlock_undo(rdev, ring);
731 	radeon_ring_unlock_commit(rdev, ring);