drm2/radeon/r600.c

2561 			  struct radeon_fence *fence)
2563 	struct radeon_ring *ring = &rdev->ring[fence->ring];
2566 		u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2580 		radeon_ring_write(ring, fence->seq);
2597 		/* Emit fence sequence & fire IRQ */
2599 		radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2600 		radeon_ring_write(ring, fence->seq);
2628  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2631  * @fence: radeon fence object
2633  * Add a DMA fence packet to the ring to write
2634  * the fence seq number and DMA trap packet to generate
2638 			      struct radeon_fence *fence)
2640 	struct radeon_ring *ring = &rdev->ring[fence->ring];
2641 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2643 	/* write the fence */
2647 	radeon_ring_write(ring, lower_32_bits(fence->seq));
2680 		   struct radeon_fence **fence)
2686 	r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2691 	r600_blit_done_copy(rdev, fence, vb, sem);
2702  * @fence: radeon fence object
2711 		  struct radeon_fence **fence)
2735 	if (radeon_fence_need_sync(*fence, ring->idx)) {
2736 		radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2738 		radeon_fence_note_sync(*fence, ring->idx);
2757 	r = radeon_fence_emit(rdev, fence, ring->idx);
2764 	radeon_semaphore_free(rdev, &sem, *fence);
3114 	r = radeon_fence_wait(ib.fence, false);
3116 		DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3126 		DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3182 	r = radeon_fence_wait(ib.fence, false);
3185 		DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3195 		DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);