drm2/radeon/r520.c

40 int r520_mc_wait_for_idle(struct radeon_device *rdev)
45 	for (i = 0; i < rdev->usec_timeout; i++) {
56 static void r520_gpu_init(struct radeon_device *rdev)
60 	rv515_vga_render_disable(rdev);
82 	if (rdev->family == CHIP_RV530) {
85 	r420_pipes_init(rdev);
92 	if (r520_mc_wait_for_idle(rdev)) {
98 static void r520_vram_get_type(struct radeon_device *rdev)
102 	rdev->mc.vram_width = 128;
103 	rdev->mc.vram_is_ddr = true;
107 		rdev->mc.vram_width = 32;
110 		rdev->mc.vram_width = 64;
113 		rdev->mc.vram_width = 128;
116 		rdev->mc.vram_width = 256;
119 		rdev->mc.vram_width = 128;
123 		rdev->mc.vram_width *= 2;
126 static void r520_mc_init(struct radeon_device *rdev)
129 	r520_vram_get_type(rdev);
130 	r100_vram_init_sizes(rdev);
131 	radeon_vram_location(rdev, &rdev->mc, 0);
132 	rdev->mc.gtt_base_align = 0;
133 	if (!(rdev->flags & RADEON_IS_AGP))
134 		radeon_gtt_location(rdev, &rdev->mc);
135 	radeon_update_bandwidth_info(rdev);
138 static void r520_mc_program(struct radeon_device *rdev)
143 	rv515_mc_stop(rdev, &save);
146 	if (r520_mc_wait_for_idle(rdev))
147 		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
149 	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
152 			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
153 			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
155 		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
156 	if (rdev->flags & RADEON_IS_AGP) {
158 			S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
159 			S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
160 		WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
162 			S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
169 	rv515_mc_resume(rdev, &save);
172 static int r520_startup(struct radeon_device *rdev)
176 	r520_mc_program(rdev);
178 	rv515_clock_startup(rdev);
180 	r520_gpu_init(rdev);
183 	if (rdev->flags & RADEON_IS_PCIE) {
184 		r = rv370_pcie_gart_enable(rdev);
190 	r = radeon_wb_init(rdev);
194 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
196 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
201 	rs600_irq_set(rdev);
202 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
204 	r = r100_cp_init(rdev, 1024 * 1024);
206 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
210 	r = radeon_ib_pool_init(rdev);
212 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
219 int r520_resume(struct radeon_device *rdev)
224 	if (rdev->flags & RADEON_IS_PCIE)
225 		rv370_pcie_gart_disable(rdev);
227 	rv515_clock_startup(rdev);
229 	if (radeon_asic_reset(rdev)) {
230 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
235 	atom_asic_init(rdev->mode_info.atom_context);
237 	rv515_clock_startup(rdev);
239 	radeon_surface_init(rdev);
241 	rdev->accel_working = true;
242 	r = r520_startup(rdev);
244 		rdev->accel_working = false;
249 int r520_init(struct radeon_device *rdev)
254 	radeon_scratch_init(rdev);
256 	radeon_surface_init(rdev);
258 	r100_restore_sanity(rdev);
261 	if (!radeon_get_bios(rdev)) {
262 		if (ASIC_IS_AVIVO(rdev))
265 	if (rdev->is_atom_bios) {
266 		r = radeon_atombios_init(rdev);
270 		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
274 	if (radeon_asic_reset(rdev)) {
275 		dev_warn(rdev->dev,
281 	if (radeon_boot_test_post_card(rdev) == false)
284 	if (!radeon_card_posted(rdev) && rdev->bios) {
286 		atom_asic_init(rdev->mode_info.atom_context);
289 	radeon_get_clock_info(rdev->ddev);
291 	if (rdev->flags & RADEON_IS_AGP) {
292 		r = radeon_agp_init(rdev);
294 			radeon_agp_disable(rdev);
298 	r520_mc_init(rdev);
299 	rv515_debugfs(rdev);
301 	r = radeon_fence_driver_init(rdev);
304 	r = radeon_irq_kms_init(rdev);
308 	r = radeon_bo_init(rdev);
311 	r = rv370_pcie_gart_init(rdev);
314 	rv515_set_safe_registers(rdev);
316 	rdev->accel_working = true;
317 	r = r520_startup(rdev);
320 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
321 		r100_cp_fini(rdev);
322 		radeon_wb_fini(rdev);
323 		radeon_ib_pool_fini(rdev);
324 		radeon_irq_kms_fini(rdev);
325 		rv370_pcie_gart_fini(rdev);
326 		radeon_agp_fini(rdev);
327 		rdev->accel_working = false;