drm2/radeon/r420.c

41 void r420_pm_init_profile(struct radeon_device *rdev)
44 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
45 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
46 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
47 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
49 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
50 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
51 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
52 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
54 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
55 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
56 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
57 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
59 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
60 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
61 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
62 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
64 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
65 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
66 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
67 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
69 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
70 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
71 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
72 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
74 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
75 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
76 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
77 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
80 static void r420_set_reg_safe(struct radeon_device *rdev)
82 	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
83 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
86 void r420_pipes_init(struct radeon_device *rdev)
96 	if (r100_gui_wait_for_idle(rdev)) {
105 	if ((rdev->ddev->pci_device == 0x5e4c) ||
106 	    (rdev->ddev->pci_device == 0x5e4f))
109 	rdev->num_gb_pipes = num_pipes;
132 	if (r100_gui_wait_for_idle(rdev)) {
145 	if (r100_gui_wait_for_idle(rdev)) {
150 	if (rdev->family == CHIP_RV530) {
153 			rdev->num_z_pipes = 2;
155 			rdev->num_z_pipes = 1;
157 		rdev->num_z_pipes = 1;
160 		 rdev->num_gb_pipes, rdev->num_z_pipes);
163 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
172 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
179 static void r420_debugfs(struct radeon_device *rdev)
181 	if (r100_debugfs_rbbm_init(rdev)) {
184 	if (r420_debugfs_pipes_info_init(rdev)) {
189 static void r420_clock_resume(struct radeon_device *rdev)
194 		radeon_atom_set_clock_gating(rdev, 1);
197 	if (rdev->family == CHIP_R420)
202 static void r420_cp_errata_init(struct radeon_device *rdev)
204 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
212 	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
213 	radeon_ring_lock(rdev, ring, 8);
215 	radeon_ring_write(ring, rdev->config.r300.resync_scratch);
217 	radeon_ring_unlock_commit(rdev, ring);
220 static void r420_cp_errata_fini(struct radeon_device *rdev)
222 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
227 	radeon_ring_lock(rdev, ring, 8);
230 	radeon_ring_unlock_commit(rdev, ring);
231 	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
234 static int r420_startup(struct radeon_device *rdev)
239 	r100_set_common_regs(rdev);
241 	r300_mc_program(rdev);
243 	r420_clock_resume(rdev);
246 	if (rdev->flags & RADEON_IS_PCIE) {
247 		r = rv370_pcie_gart_enable(rdev);
251 	if (rdev->flags & RADEON_IS_PCI) {
252 		r = r100_pci_gart_enable(rdev);
256 	r420_pipes_init(rdev);
259 	r = radeon_wb_init(rdev);
263 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
265 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
270 	r100_irq_set(rdev);
271 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
273 	r = r100_cp_init(rdev, 1024 * 1024);
275 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
278 	r420_cp_errata_init(rdev);
280 	r = radeon_ib_pool_init(rdev);
282 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
289 int r420_resume(struct radeon_device *rdev)
294 	if (rdev->flags & RADEON_IS_PCIE)
295 		rv370_pcie_gart_disable(rdev);
296 	if (rdev->flags & RADEON_IS_PCI)
297 		r100_pci_gart_disable(rdev);
299 	r420_clock_resume(rdev);
301 	if (radeon_asic_reset(rdev)) {
302 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
307 	if (rdev->is_atom_bios) {
308 		atom_asic_init(rdev->mode_info.atom_context);
310 		radeon_combios_asic_init(rdev->ddev);
313 	r420_clock_resume(rdev);
315 	radeon_surface_init(rdev);
317 	rdev->accel_working = true;
318 	r = r420_startup(rdev);
320 		rdev->accel_working = false;
325 int r420_suspend(struct radeon_device *rdev)
327 	r420_cp_errata_fini(rdev);
328 	r100_cp_disable(rdev);
329 	radeon_wb_disable(rdev);
330 	r100_irq_disable(rdev);
331 	if (rdev->flags & RADEON_IS_PCIE)
332 		rv370_pcie_gart_disable(rdev);
333 	if (rdev->flags & RADEON_IS_PCI)
334 		r100_pci_gart_disable(rdev);
338 void r420_fini(struct radeon_device *rdev)
340 	r100_cp_fini(rdev);
341 	radeon_wb_fini(rdev);
342 	radeon_ib_pool_fini(rdev);
343 	radeon_gem_fini(rdev);
344 	if (rdev->flags & RADEON_IS_PCIE)
345 		rv370_pcie_gart_fini(rdev);
346 	if (rdev->flags & RADEON_IS_PCI)
347 		r100_pci_gart_fini(rdev);
348 	radeon_agp_fini(rdev);
349 	radeon_irq_kms_fini(rdev);
350 	radeon_fence_driver_fini(rdev);
351 	radeon_bo_fini(rdev);
352 	if (rdev->is_atom_bios) {
353 		radeon_atombios_fini(rdev);
355 		radeon_combios_fini(rdev);
357 	free(rdev->bios, DRM_MEM_DRIVER);
358 	rdev->bios = NULL;
361 int r420_init(struct radeon_device *rdev)
366 	radeon_scratch_init(rdev);
368 	radeon_surface_init(rdev);
371 	r100_restore_sanity(rdev);
373 	if (!radeon_get_bios(rdev)) {
374 		if (ASIC_IS_AVIVO(rdev))
377 	if (rdev->is_atom_bios) {
378 		r = radeon_atombios_init(rdev);
383 		r = radeon_combios_init(rdev);
389 	if (radeon_asic_reset(rdev)) {
390 		dev_warn(rdev->dev,
396 	if (radeon_boot_test_post_card(rdev) == false)
400 	radeon_get_clock_info(rdev->ddev);
402 	if (rdev->flags & RADEON_IS_AGP) {
403 		r = radeon_agp_init(rdev);
405 			radeon_agp_disable(rdev);
409 	r300_mc_init(rdev);
410 	r420_debugfs(rdev);
412 	r = radeon_fence_driver_init(rdev);
416 	r = radeon_irq_kms_init(rdev);
421 	r = radeon_bo_init(rdev);
425 	if (rdev->family == CHIP_R420)
426 		r100_enable_bm(rdev);
428 	if (rdev->flags & RADEON_IS_PCIE) {
429 		r = rv370_pcie_gart_init(rdev);
433 	if (rdev->flags & RADEON_IS_PCI) {
434 		r = r100_pci_gart_init(rdev);
438 	r420_set_reg_safe(rdev);
440 	rdev->accel_working = true;
441 	r = r420_startup(rdev);
444 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
445 		r100_cp_fini(rdev);
446 		radeon_wb_fini(rdev);
447 		radeon_ib_pool_fini(rdev);
448 		radeon_irq_kms_fini(rdev);
449 		if (rdev->flags & RADEON_IS_PCIE)
450 			rv370_pcie_gart_fini(rdev);
451 		if (rdev->flags & RADEON_IS_PCI)
452 			r100_pci_gart_fini(rdev);
453 		radeon_agp_fini(rdev);
454 		rdev->accel_working = false;
467 	struct radeon_device *rdev = dev->dev_private;
484 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
487 	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);