Lines Matching refs:ring
910 int ring, u32 cp_int_cntl)
914 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
924 struct radeon_ring *ring = &rdev->ring[fence->ring];
925 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
928 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
929 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
930 radeon_ring_write(ring, 0);
931 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
932 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
933 radeon_ring_write(ring, 0xFFFFFFFF);
934 radeon_ring_write(ring, 0);
935 radeon_ring_write(ring, 10); /* poll interval */
937 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
938 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
939 radeon_ring_write(ring, addr & 0xffffffff);
940 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
941 radeon_ring_write(ring, fence->seq);
942 radeon_ring_write(ring, 0);
947 struct radeon_ring *ring = &rdev->ring[ib->ring];
950 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
951 radeon_ring_write(ring, 1);
953 if (ring->rptr_save_reg) {
954 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
955 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
956 radeon_ring_write(ring, ((ring->rptr_save_reg -
958 radeon_ring_write(ring, next_rptr);
961 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
962 radeon_ring_write(ring,
967 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
968 radeon_ring_write(ring, ib->length_dw |
972 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
973 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
974 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
975 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
976 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
977 radeon_ring_write(ring, 0xFFFFFFFF);
978 radeon_ring_write(ring, 0);
979 radeon_ring_write(ring, 10); /* poll interval */
990 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1023 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1026 r = radeon_ring_lock(rdev, ring, 7);
1028 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1031 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1032 radeon_ring_write(ring, 0x1);
1033 radeon_ring_write(ring, 0x0);
1034 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1035 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1036 radeon_ring_write(ring, 0);
1037 radeon_ring_write(ring, 0);
1038 radeon_ring_unlock_commit(rdev, ring);
1042 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1044 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1049 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1050 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1053 radeon_ring_write(ring, cayman_default_state[i]);
1055 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1056 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1059 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1060 radeon_ring_write(ring, 0);
1063 radeon_ring_write(ring, 0xc0026f00);
1064 radeon_ring_write(ring, 0x00000000);
1065 radeon_ring_write(ring, 0x00000000);
1066 radeon_ring_write(ring, 0x00000000);
1069 radeon_ring_write(ring, 0xc0036f00);
1070 radeon_ring_write(ring, 0x00000bc4);
1071 radeon_ring_write(ring, 0xffffffff);
1072 radeon_ring_write(ring, 0xffffffff);
1073 radeon_ring_write(ring, 0xffffffff);
1075 radeon_ring_write(ring, 0xc0026900);
1076 radeon_ring_write(ring, 0x00000316);
1077 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1078 radeon_ring_write(ring, 0x00000010); /* */
1080 radeon_ring_unlock_commit(rdev, ring);
1089 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1091 radeon_ring_fini(rdev, ring);
1092 radeon_scratch_free(rdev, ring->rptr_save_reg);
1122 struct radeon_ring *ring;
1153 /* Set ring buffer size */
1154 ring = &rdev->ring[ridx[i]];
1155 rb_cntl = drm_order(ring->ring_size / 8);
1170 ring = &rdev->ring[ridx[i]];
1171 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1175 /* Initialize the ring buffer's read and write pointers */
1176 ring = &rdev->ring[ridx[i]];
1179 ring->rptr = ring->wptr = 0;
1180 WREG32(ring->rptr_reg, ring->rptr);
1181 WREG32(ring->wptr_reg, ring->wptr);
1189 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1190 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1191 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1193 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1195 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1196 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1197 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1208 * to the 3D engine (ring buffer, IBs, etc.), but the
1222 * Schedule an IB in the DMA ring (cayman-SI).
1227 struct radeon_ring *ring = &rdev->ring[ib->ring];
1230 u32 next_rptr = ring->wptr + 4;
1234 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1235 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1236 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1237 radeon_ring_write(ring, next_rptr);
1240 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1243 while ((ring->wptr & 7) != 5)
1244 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1245 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1246 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1247 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1274 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1275 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1283 * Set up the DMA ring buffers and enable them. (cayman-SI).
1288 struct radeon_ring *ring;
1302 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1306 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1314 /* Set ring buffer size in dwords */
1315 rb_bufsz = drm_order(ring->ring_size / 4);
1322 /* Initialize the ring buffer's read and write pointers */
1335 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1348 ring->wptr = 0;
1349 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1351 ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1355 ring->ready = true;
1357 r = radeon_ring_test(rdev, ring->idx, ring);
1359 ring->ready = false;
1379 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1380 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1535 * @ring: radeon_ring structure holding ring information
1540 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1544 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
1549 radeon_ring_lockup_update(ring);
1552 /* force ring activities */
1553 radeon_ring_force_activity(rdev, ring);
1554 return radeon_ring_test_lockup(rdev, ring);
1559 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1659 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1665 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1666 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1673 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1674 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1752 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1801 ring->ring_obj = NULL;
1802 r600_ring_init(rdev, ring, 1024 * 1024);
1804 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1805 ring->ring_obj = NULL;
1806 r600_ring_init(rdev, ring, 64 * 1024);
1808 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1809 ring->ring_obj = NULL;
1810 r600_ring_init(rdev, ring, 64 * 1024);
1930 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
1941 radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
1942 radeon_ring_write(ring, pe);
1943 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1955 radeon_ring_write(ring, value);
1956 radeon_ring_write(ring, upper_32_bits(value));
1966 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw));
1967 radeon_ring_write(ring, pe);
1968 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1980 radeon_ring_write(ring, value);
1981 radeon_ring_write(ring, upper_32_bits(value));
1997 struct radeon_ring *ring = &rdev->ring[ridx];
2002 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2003 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2006 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2007 radeon_ring_write(ring, 0x1);
2010 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2011 radeon_ring_write(ring, 1 << vm->id);
2014 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2015 radeon_ring_write(ring, 0x0);
2020 struct radeon_ring *ring = &rdev->ring[ridx];
2025 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2026 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
2027 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2030 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2031 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
2032 radeon_ring_write(ring, 1);
2035 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2036 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
2037 radeon_ring_write(ring, 1 << vm->id);