Lines Matching refs:offset
48 uint32_t offset = dig->afmt->offset;
50 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
51 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
53 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
54 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
56 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
57 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
103 uint32_t offset = dig->afmt->offset;
142 WREG32(AFMT_AVI_INFO0 + offset,
144 WREG32(AFMT_AVI_INFO1 + offset,
146 WREG32(AFMT_AVI_INFO2 + offset,
148 WREG32(AFMT_AVI_INFO3 + offset,
161 uint32_t offset;
166 offset = dig->afmt->offset;
170 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
173 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
175 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
179 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
183 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
187 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
192 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
198 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
201 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
205 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
213 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
214 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
215 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
216 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);