drm2/radeon/evergreen_cs.c

2895 	u64 src_offset, dst_offset, dst2_offset;
2969 						src_offset = radeon_get_ib_value(p, idx+8);
2970 						src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
2971 						if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2973 								 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3029 						src_offset = radeon_get_ib_value(p, idx+8);
3030 						src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
3031 						if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3033 								 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3057 							src_offset = radeon_get_ib_value(p, idx+1);
3058 							src_offset <<= 8;
3067 							src_offset = radeon_get_ib_value(p, idx+7);
3068 							src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3076 						if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3078 								 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3113 						src_offset = radeon_get_ib_value(p, idx+8);
3114 						src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
3115 						if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3117 								 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3146 							src_offset = radeon_get_ib_value(p, idx+1);
3147 							src_offset <<= 8;
3156 							src_offset = radeon_get_ib_value(p, idx+7);
3157 							src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3165 						if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3167 								 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3187 						src_offset = radeon_get_ib_value(p, idx+2);
3188 						src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
3191 						if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
3193 								 (uintmax_t)src_offset + count, radeon_bo_size(src_reloc->robj));
3231 						src_offset = radeon_get_ib_value(p, idx+3);
3232 						src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
3233 						if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3235 								 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3262 					src_offset = radeon_get_ib_value(p, idx+2);
3263 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
3266 					if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3268 							 (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));