drm2/radeon/evergreen_cs.c

1364 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1395 			ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1396 			track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1397 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1400 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1436 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1448 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1460 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1472 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1496 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1516 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1580 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1581 			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1598 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1599 			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1660 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1663 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1688 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1691 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1719 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1736 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1777 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1793 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1805 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1922 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1936 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1950 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2035 		offset = reloc->lobj.gpu_offset +
2081 		offset = reloc->lobj.gpu_offset +
2108 		offset = reloc->lobj.gpu_offset +
2136 		offset = reloc->lobj.gpu_offset +
2226 		ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2248 			offset = reloc->lobj.gpu_offset +
2302 				offset = reloc->lobj.gpu_offset + tmp;
2340 				offset = reloc->lobj.gpu_offset + tmp;
2370 			ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2386 			offset = reloc->lobj.gpu_offset +
2408 		offset = reloc->lobj.gpu_offset +
2430 		offset = reloc->lobj.gpu_offset +
2498 						TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2499 					if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
2502 						evergreen_tiling_fields(reloc->lobj.tiling_flags,
2514 				toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2533 					moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2560 				offset64 = reloc->lobj.gpu_offset + offset;
2641 			offset += reloc->lobj.gpu_offset;
2660 			offset += reloc->lobj.gpu_offset;
2689 		offset += reloc->lobj.gpu_offset;
2714 			offset += reloc->lobj.gpu_offset;
2738 			offset += reloc->lobj.gpu_offset;
2923 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2929 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2930 				ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2986 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2987 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2988 						ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2989 						ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3001 							ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3003 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3004 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3007 							ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3008 							ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3010 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3046 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3047 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
3048 						ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3049 						ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3059 							ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3063 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3064 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3069 							ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3070 							ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3074 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3094 						ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3095 						ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3130 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3131 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
3132 						ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3133 						ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3148 							ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3152 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3153 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3158 							ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3159 							ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3163 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3201 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3202 						ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3203 						ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3204 						ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3213 						ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3214 						ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3215 						ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3216 						ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3248 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3249 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
3250 						ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3251 						ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3252 						ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
3253 						ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3276 					ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3277 					ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3278 					ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3279 					ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3297 			ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3298 			ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;