drm2/radeon/evergreen_cs.c

2895 	u64 src_offset, dst_offset, dst2_offset;
2920 				dst_offset = radeon_get_ib_value(p, idx+1);
2921 				dst_offset <<= 8;
2926 				dst_offset = radeon_get_ib_value(p, idx+1);
2927 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2933 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2935 					 (uintmax_t)dst_offset, radeon_bo_size(dst_reloc->robj));
2965 						dst_offset = radeon_get_ib_value(p, idx+1);
2966 						dst_offset <<= 8;
2976 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2978 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3025 						dst_offset = radeon_get_ib_value(p, idx+1);
3026 						dst_offset <<= 8;
3036 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3038 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3061 							dst_offset = radeon_get_ib_value(p, idx+7);
3062 							dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3072 							dst_offset = radeon_get_ib_value(p, idx+1);
3073 							dst_offset <<= 8;
3081 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3083 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3109 						dst_offset = radeon_get_ib_value(p, idx+1);
3110 						dst_offset <<= 8;
3120 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3122 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3150 							dst_offset = radeon_get_ib_value(p, idx+7);
3151 							dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3161 							dst_offset = radeon_get_ib_value(p, idx+1);
3162 							dst_offset <<= 8;
3170 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3172 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3189 						dst_offset = radeon_get_ib_value(p, idx+1);
3190 						dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
3196 						if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
3198 								 (uintmax_t)dst_offset + count, radeon_bo_size(dst_reloc->robj));
3227 						dst_offset = radeon_get_ib_value(p, idx+1);
3228 						dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
3238 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3240 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3264 					dst_offset = radeon_get_ib_value(p, idx+1);
3265 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
3271 					if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3273 							 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3290 			dst_offset = radeon_get_ib_value(p, idx+1);
3291 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
3292 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3294 					 (uintmax_t)dst_offset, radeon_bo_size(dst_reloc->robj));