drm2/radeon/evergreen_blit_kms.c

45 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
59 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
60 	radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
61 	radeon_ring_write(ring, gpu_addr >> 8);
62 	radeon_ring_write(ring, pitch);
63 	radeon_ring_write(ring, slice);
64 	radeon_ring_write(ring, 0);
65 	radeon_ring_write(ring, cb_color_info);
66 	radeon_ring_write(ring, 0);
67 	radeon_ring_write(ring, (w - 1) | ((h - 1) << 16));
68 	radeon_ring_write(ring, 0);
69 	radeon_ring_write(ring, 0);
70 	radeon_ring_write(ring, 0);
71 	radeon_ring_write(ring, 0);
72 	radeon_ring_write(ring, 0);
73 	radeon_ring_write(ring, 0);
74 	radeon_ring_write(ring, 0);
75 	radeon_ring_write(ring, 0);
84 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
97 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
98 		radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
99 		radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */
101 	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
102 	radeon_ring_write(ring, sync_type);
103 	radeon_ring_write(ring, cp_coher_size);
104 	radeon_ring_write(ring, mc_addr >> 8);
105 	radeon_ring_write(ring, 10); /* poll interval */
112 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
117 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
118 	radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
119 	radeon_ring_write(ring, gpu_addr >> 8);
120 	radeon_ring_write(ring, 2);
121 	radeon_ring_write(ring, 0);
125 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
126 	radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
127 	radeon_ring_write(ring, gpu_addr >> 8);
128 	radeon_ring_write(ring, 1);
129 	radeon_ring_write(ring, 0);
130 	radeon_ring_write(ring, 2);
140 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
155 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
156 	radeon_ring_write(ring, 0x580);
157 	radeon_ring_write(ring, gpu_addr & 0xffffffff);
158 	radeon_ring_write(ring, 48 - 1); /* size */
159 	radeon_ring_write(ring, sq_vtx_constant_word2);
160 	radeon_ring_write(ring, sq_vtx_constant_word3);
161 	radeon_ring_write(ring, 0);
162 	radeon_ring_write(ring, 0);
163 	radeon_ring_write(ring, 0);
164 	radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
185 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
209 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
210 	radeon_ring_write(ring, 0);
211 	radeon_ring_write(ring, sq_tex_resource_word0);
212 	radeon_ring_write(ring, sq_tex_resource_word1);
213 	radeon_ring_write(ring, gpu_addr >> 8);
214 	radeon_ring_write(ring, gpu_addr >> 8);
215 	radeon_ring_write(ring, sq_tex_resource_word4);
216 	radeon_ring_write(ring, 0);
217 	radeon_ring_write(ring, 0);
218 	radeon_ring_write(ring, sq_tex_resource_word7);
226 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
237 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
238 	radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
239 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
240 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
242 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
243 	radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
244 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
245 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
247 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
248 	radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
249 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
250 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
257 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
258 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
259 	radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
260 	radeon_ring_write(ring, DI_PT_RECTLIST);
262 	radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
263 	radeon_ring_write(ring,
269 	radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
270 	radeon_ring_write(ring, 1);
272 	radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
273 	radeon_ring_write(ring, 3);
274 	radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
282 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
296 	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
297 	radeon_ring_write(ring, 0);
554 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
555 		radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
556 		radeon_ring_write(ring, 0);
559 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
560 		radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
561 		radeon_ring_write(ring, 0x10001000);
564 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11));
565 		radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
566 		radeon_ring_write(ring, sq_config);
567 		radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
568 		radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
569 		radeon_ring_write(ring, sq_gpr_resource_mgmt_3);
570 		radeon_ring_write(ring, 0);
571 		radeon_ring_write(ring, 0);
572 		radeon_ring_write(ring, sq_thread_resource_mgmt);
573 		radeon_ring_write(ring, sq_thread_resource_mgmt_2);
574 		radeon_ring_write(ring, sq_stack_resource_mgmt_1);
575 		radeon_ring_write(ring, sq_stack_resource_mgmt_2);
576 		radeon_ring_write(ring, sq_stack_resource_mgmt_3);
580 	radeon_ring_write(ring, 0xc0012800);
581 	radeon_ring_write(ring, 0x80000000);
582 	radeon_ring_write(ring, 0x80000000);
585 	radeon_ring_write(ring, 0xc0026f00);
586 	radeon_ring_write(ring, 0x00000000);
587 	radeon_ring_write(ring, 0x00000000);
588 	radeon_ring_write(ring, 0x00000000);
591 	radeon_ring_write(ring, 0xc0036e00);
592 	radeon_ring_write(ring, 0x00000000);
593 	radeon_ring_write(ring, 0x00000012);
594 	radeon_ring_write(ring, 0x00000000);
595 	radeon_ring_write(ring, 0x00000000);
598 	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
599 	radeon_ring_write(ring, 1);
604 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
605 	radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC);
606 	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
607 	radeon_ring_write(ring, dwords);