Lines Matching refs:tmp
220 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
224 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
225 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
247 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
248 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
479 u32 tmp;
485 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
486 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
487 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
504 u32 tmp;
510 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
511 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
512 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
573 u32 tmp;
578 tmp = RREG32(DC_HPD1_INT_CONTROL);
580 tmp &= ~DC_HPDx_INT_POLARITY;
582 tmp |= DC_HPDx_INT_POLARITY;
583 WREG32(DC_HPD1_INT_CONTROL, tmp);
586 tmp = RREG32(DC_HPD2_INT_CONTROL);
588 tmp &= ~DC_HPDx_INT_POLARITY;
590 tmp |= DC_HPDx_INT_POLARITY;
591 WREG32(DC_HPD2_INT_CONTROL, tmp);
594 tmp = RREG32(DC_HPD3_INT_CONTROL);
596 tmp &= ~DC_HPDx_INT_POLARITY;
598 tmp |= DC_HPDx_INT_POLARITY;
599 WREG32(DC_HPD3_INT_CONTROL, tmp);
602 tmp = RREG32(DC_HPD4_INT_CONTROL);
604 tmp &= ~DC_HPDx_INT_POLARITY;
606 tmp |= DC_HPDx_INT_POLARITY;
607 WREG32(DC_HPD4_INT_CONTROL, tmp);
610 tmp = RREG32(DC_HPD5_INT_CONTROL);
612 tmp &= ~DC_HPDx_INT_POLARITY;
614 tmp |= DC_HPDx_INT_POLARITY;
615 WREG32(DC_HPD5_INT_CONTROL, tmp);
618 tmp = RREG32(DC_HPD6_INT_CONTROL);
620 tmp &= ~DC_HPDx_INT_POLARITY;
622 tmp |= DC_HPDx_INT_POLARITY;
623 WREG32(DC_HPD6_INT_CONTROL, tmp);
643 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
660 WREG32(DC_HPD1_CONTROL, tmp);
663 WREG32(DC_HPD2_CONTROL, tmp);
666 WREG32(DC_HPD3_CONTROL, tmp);
669 WREG32(DC_HPD4_CONTROL, tmp);
672 WREG32(DC_HPD5_CONTROL, tmp);
675 WREG32(DC_HPD6_CONTROL, tmp);
736 u32 tmp;
760 tmp = 0; /* 1/2 */
762 tmp = 2; /* whole */
764 tmp = 0;
768 tmp += 4;
769 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
772 switch (tmp) {
807 u32 tmp = RREG32(MC_SHARED_CHMAP);
809 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1062 u32 tmp, arb_control3;
1133 tmp = arb_control3;
1134 tmp &= ~LATENCY_WATERMARK_MASK(3);
1135 tmp |= LATENCY_WATERMARK_MASK(1);
1136 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1141 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1142 tmp &= ~LATENCY_WATERMARK_MASK(3);
1143 tmp |= LATENCY_WATERMARK_MASK(2);
1144 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1200 u32 tmp;
1204 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1205 if (!tmp)
1218 u32 tmp;
1225 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1226 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1227 if (tmp == 2) {
1231 if (tmp) {
1240 u32 tmp;
1258 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1263 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1264 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1265 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1267 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1268 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1269 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1274 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1276 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1277 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1278 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1279 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1299 u32 tmp;
1311 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1312 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1313 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1314 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1315 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1316 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1317 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1318 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1332 u32 tmp;
1341 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1345 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1346 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1347 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1348 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1349 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1350 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1351 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1358 u32 crtc_enabled, tmp, frame_count, blackout;
1372 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1373 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1376 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1377 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1380 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1381 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1384 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1385 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1399 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1400 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
1401 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1426 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1427 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
1428 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
1429 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
1431 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
1432 if (!(tmp & 1)) {
1433 tmp |= 1;
1434 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
1442 u32 tmp, frame_count;
1462 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
1463 if ((tmp & 0x3) != 0) {
1464 tmp &= ~0x3;
1465 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
1467 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1468 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
1469 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
1470 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
1472 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
1473 if (tmp & 1) {
1474 tmp &= ~1;
1475 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
1478 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1479 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
1487 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1488 tmp &= ~BLACKOUT_MODE_MASK;
1489 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1496 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1497 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1499 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1502 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1503 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1505 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1526 u32 tmp;
1571 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1572 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1573 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1574 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1576 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1577 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1578 WREG32(MC_VM_FB_LOCATION, tmp);
1739 u32 tmp;
1757 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1759 tmp |= BUF_SWAP_32BIT;
1761 WREG32(CP_RB_CNTL, tmp);
1769 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1783 tmp |= RB_NO_UPDATE;
1788 WREG32(CP_RB_CNTL, tmp);
1825 u32 hdp_host_path_cntl, tmp;
2135 tmp = (((efuse_straps_4 & 0xf) << 4) |
2138 tmp = 0;
2145 tmp <<= 4;
2146 tmp |= rb_disable_bitmap;
2150 disabled_rb_mask = tmp;
2164 tmp = 0x11111111;
2167 tmp = 0x00000000;
2170 tmp = gb_addr_config & NUM_PIPES_MASK;
2171 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2174 WREG32(GB_BACKEND_MAP, tmp);
2350 tmp = RREG32(HDP_MISC_CNTL);
2351 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2352 WREG32(HDP_MISC_CNTL, tmp);
2365 u32 tmp;
2373 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2375 tmp = RREG32(MC_ARB_RAMCFG);
2376 if (tmp & CHANSIZE_OVERRIDE) {
2378 } else if (tmp & CHANSIZE_MASK) {
2383 tmp = RREG32(MC_SHARED_CHMAP);
2384 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2509 u32 tmp;
2518 tmp = RREG32(DMA_RB_CNTL);
2519 tmp &= ~DMA_RB_ENABLE;
2520 WREG32(DMA_RB_CNTL, tmp);
2584 u32 tmp;
2591 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2592 WREG32(CAYMAN_DMA1_CNTL, tmp);
2595 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2596 WREG32(DMA_CNTL, tmp);
2625 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2626 WREG32(DC_HPD1_INT_CONTROL, tmp);
2627 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2628 WREG32(DC_HPD2_INT_CONTROL, tmp);
2629 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2630 WREG32(DC_HPD3_INT_CONTROL, tmp);
2631 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2632 WREG32(DC_HPD4_INT_CONTROL, tmp);
2633 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2634 WREG32(DC_HPD5_INT_CONTROL, tmp);
2635 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2636 WREG32(DC_HPD6_INT_CONTROL, tmp);
2848 u32 tmp;
2918 tmp = RREG32(DC_HPD1_INT_CONTROL);
2919 tmp |= DC_HPDx_INT_ACK;
2920 WREG32(DC_HPD1_INT_CONTROL, tmp);
2923 tmp = RREG32(DC_HPD2_INT_CONTROL);
2924 tmp |= DC_HPDx_INT_ACK;
2925 WREG32(DC_HPD2_INT_CONTROL, tmp);
2928 tmp = RREG32(DC_HPD3_INT_CONTROL);
2929 tmp |= DC_HPDx_INT_ACK;
2930 WREG32(DC_HPD3_INT_CONTROL, tmp);
2933 tmp = RREG32(DC_HPD4_INT_CONTROL);
2934 tmp |= DC_HPDx_INT_ACK;
2935 WREG32(DC_HPD4_INT_CONTROL, tmp);
2938 tmp = RREG32(DC_HPD5_INT_CONTROL);
2939 tmp |= DC_HPDx_INT_ACK;
2940 WREG32(DC_HPD5_INT_CONTROL, tmp);
2943 tmp = RREG32(DC_HPD5_INT_CONTROL);
2944 tmp |= DC_HPDx_INT_ACK;
2945 WREG32(DC_HPD6_INT_CONTROL, tmp);
2948 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2949 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2950 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2953 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2954 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2955 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2958 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2959 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2960 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2963 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2964 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2965 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2968 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2969 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2970 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2973 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2974 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2975 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2996 u32 wptr, tmp;
3011 tmp = RREG32(IH_RB_CNTL);
3012 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3013 WREG32(IH_RB_CNTL, tmp);