drm2/radeon/evergreen.c

838 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
846 	yclk.full = dfixed_const(wm->yclk);
848 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
858 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
866 	yclk.full = dfixed_const(wm->yclk);
868 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
878 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
886 	sclk.full = dfixed_const(wm->sclk);
898 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
906 	disp_clk.full = dfixed_const(wm->disp_clk);
918 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
921 	u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
922 	u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
923 	u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
928 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
941 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
943 	bpp.full = dfixed_const(wm->bytes_per_pixel);
944 	src_width.full = dfixed_const(wm->src_width);
946 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
952 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
956 	u32 available_bandwidth = evergreen_available_bandwidth(wm);
959 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
960 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
961 		(wm->num_heads * cursor_line_pair_return_time);
966 	if (wm->num_heads == 0)
971 	if ((wm->vsc.full > a.full) ||
972 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
973 	    (wm->vtaps >= 5) ||
974 	    ((wm->vsc.full >= a.full) && wm->interlaced))
980 	b.full = dfixed_const(wm->num_heads);
984 	c.full = dfixed_const(wm->disp_clk);
986 	c.full = dfixed_const(wm->bytes_per_pixel);
991 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
998 	if (line_fill_time < wm->active_time)
1001 		return latency + (line_fill_time - wm->active_time);
1005 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
1007 	if (evergreen_average_bandwidth(wm) <=
1008 	    (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
1014 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
1016 	if (evergreen_average_bandwidth(wm) <=
1017 	    (evergreen_available_bandwidth(wm) / wm->num_heads))
1023 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
1025 	u32 lb_partitions = wm->lb_size / wm->src_width;
1026 	u32 line_time = wm->active_time + wm->blank_time;
1032 	if (wm->vsc.full > a.full)
1035 		if (lb_partitions <= (wm->vtaps + 1))
1041 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1043 	if (evergreen_latency_watermark(wm) <= latency_hiding)
1054 	struct evergreen_wm_params wm;
1071 		wm.yclk = rdev->pm.current_mclk * 10;
1072 		wm.sclk = rdev->pm.current_sclk * 10;
1073 		wm.disp_clk = mode->clock;
1074 		wm.src_width = mode->crtc_hdisplay;
1075 		wm.active_time = mode->crtc_hdisplay * pixel_period;
1076 		wm.blank_time = line_time - wm.active_time;
1077 		wm.interlaced = false;
1079 			wm.interlaced = true;
1080 		wm.vsc = radeon_crtc->vsc;
1081 		wm.vtaps = 1;
1083 			wm.vtaps = 2;
1084 		wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1085 		wm.lb_size = lb_size;
1086 		wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1087 		wm.num_heads = num_heads;
1090 		latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1092 		/* wm.yclk = low clk; wm.sclk = low clk */
1093 		latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1097 		if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1098 		    !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1099 		    !evergreen_check_latency_hiding(&wm) ||
1131 	/* select wm A */
1140 	/* select wm B */