Lines Matching refs:dpcd
360 u8 dpcd[DP_DPCD_SIZE],
364 int max_link_rate = drm_dp_max_link_rate(dpcd);
365 int max_lane_num = drm_dp_max_lane_count(dpcd);
379 u8 dpcd[DP_DPCD_SIZE],
389 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
402 return drm_dp_max_link_rate(dpcd);
438 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
459 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
469 dig_connector->dpcd[0] = 0;
519 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
521 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
537 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
581 u8 dpcd[DP_RECEIVER_CAP_SIZE];
642 if (dp_info->dpcd[0] >= 0x11)
647 if (dp_info->dpcd[3] & 0x1)
661 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
662 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
723 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
785 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
876 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);