Lines Matching refs:ring
50 static inline int ring_space(struct intel_ring_buffer *ring)
52 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
54 space += ring->size;
59 gen2_render_ring_flush(struct intel_ring_buffer *ring,
73 ret = intel_ring_begin(ring, 2);
77 intel_ring_emit(ring, cmd);
78 intel_ring_emit(ring, MI_NOOP);
79 intel_ring_advance(ring);
85 gen4_render_ring_flush(struct intel_ring_buffer *ring,
89 struct drm_device *dev = ring->dev;
131 ret = intel_ring_begin(ring, 2);
135 intel_ring_emit(ring, cmd);
136 intel_ring_emit(ring, MI_NOOP);
137 intel_ring_advance(ring);
180 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
182 struct pipe_control *pc = ring->private;
187 ret = intel_ring_begin(ring, 6);
191 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
192 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
194 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
195 intel_ring_emit(ring, 0); /* low dword */
196 intel_ring_emit(ring, 0); /* high dword */
197 intel_ring_emit(ring, MI_NOOP);
198 intel_ring_advance(ring);
200 ret = intel_ring_begin(ring, 6);
204 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
205 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
206 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
207 intel_ring_emit(ring, 0);
208 intel_ring_emit(ring, 0);
209 intel_ring_emit(ring, MI_NOOP);
210 intel_ring_advance(ring);
216 gen6_render_ring_flush(struct intel_ring_buffer *ring,
220 struct pipe_control *pc = ring->private;
225 ret = intel_emit_post_sync_nonzero_flush(ring);
255 ret = intel_ring_begin(ring, 4);
259 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
260 intel_ring_emit(ring, flags);
261 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
262 intel_ring_emit(ring, 0);
263 intel_ring_advance(ring);
269 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
273 ret = intel_ring_begin(ring, 4);
277 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
280 intel_ring_emit(ring, 0);
281 intel_ring_emit(ring, 0);
282 intel_ring_advance(ring);
288 gen7_render_ring_flush(struct intel_ring_buffer *ring,
292 struct pipe_control *pc = ring->private;
329 gen7_render_ring_cs_stall_wa(ring);
332 ret = intel_ring_begin(ring, 4);
336 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
337 intel_ring_emit(ring, flags);
338 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
339 intel_ring_emit(ring, 0);
340 intel_ring_advance(ring);
345 static void ring_write_tail(struct intel_ring_buffer *ring,
348 drm_i915_private_t *dev_priv = ring->dev->dev_private;
349 I915_WRITE_TAIL(ring, value);
352 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
354 drm_i915_private_t *dev_priv = ring->dev->dev_private;
355 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
356 RING_ACTHD(ring->mmio_base) : ACTHD;
361 static int init_ring_common(struct intel_ring_buffer *ring)
363 struct drm_device *dev = ring->dev;
365 struct drm_i915_gem_object *obj = ring->obj;
372 /* Stop the ring if it's running. */
373 I915_WRITE_CTL(ring, 0);
374 I915_WRITE_HEAD(ring, 0);
375 ring->write_tail(ring, 0);
377 head = I915_READ_HEAD(ring) & HEAD_ADDR;
379 /* G45 ring initialization fails to reset head to zero */
383 ring->name,
384 I915_READ_CTL(ring),
385 I915_READ_HEAD(ring),
386 I915_READ_TAIL(ring),
387 I915_READ_START(ring));
389 I915_WRITE_HEAD(ring, 0);
391 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
394 ring->name,
395 I915_READ_CTL(ring),
396 I915_READ_HEAD(ring),
397 I915_READ_TAIL(ring),
398 I915_READ_START(ring));
402 /* Initialize the ring. This must happen _after_ we've cleared the ring
404 * also enforces ordering), otherwise the hw might lose the new ring
406 I915_WRITE_START(ring, obj->gtt_offset);
407 I915_WRITE_CTL(ring,
408 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
411 /* If the head is still not zero, the ring is dead */
412 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
413 I915_READ_START(ring) == obj->gtt_offset &&
414 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
417 ring->name,
418 I915_READ_CTL(ring),
419 I915_READ_HEAD(ring),
420 I915_READ_TAIL(ring),
421 I915_READ_START(ring));
426 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
427 i915_kernel_lost_context(ring->dev);
429 ring->head = I915_READ_HEAD(ring);
430 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
431 ring->space = ring_space(ring);
432 ring->last_retired_head = -1;
443 init_pipe_control(struct intel_ring_buffer *ring)
449 if (ring->private)
456 obj = i915_gem_alloc_object(ring->dev, 4096);
478 ring->private = pc;
491 cleanup_pipe_control(struct intel_ring_buffer *ring)
493 struct pipe_control *pc = ring->private;
496 if (!ring->private)
507 ring->private = NULL;
510 static int init_render_ring(struct intel_ring_buffer *ring)
512 struct drm_device *dev = ring->dev;
514 int ret = init_ring_common(ring);
537 ret = init_pipe_control(ring);
555 ring->itlb_before_ctx_switch =
563 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
568 static void render_ring_cleanup(struct intel_ring_buffer *ring)
570 struct drm_device *dev = ring->dev;
572 if (!ring->private)
576 drm_gem_object_unreference(to_gem_object(ring->private));
578 cleanup_pipe_control(ring);
582 update_mboxes(struct intel_ring_buffer *ring,
585 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
586 intel_ring_emit(ring, mmio_offset);
587 intel_ring_emit(ring, ring->outstanding_lazy_request);
593 * @ring - ring that is adding a request
594 * @seqno - return seqno stuck into the ring
600 gen6_add_request(struct intel_ring_buffer *ring)
606 ret = intel_ring_begin(ring, 10);
610 mbox1_reg = ring->signal_mbox[0];
611 mbox2_reg = ring->signal_mbox[1];
613 update_mboxes(ring, mbox1_reg);
614 update_mboxes(ring, mbox2_reg);
615 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
616 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
617 intel_ring_emit(ring, ring->outstanding_lazy_request);
618 intel_ring_emit(ring, MI_USER_INTERRUPT);
619 intel_ring_advance(ring);
627 * @waiter - ring that is waiting
628 * @signaller - ring which has, or will signal
674 pc_render_add_request(struct intel_ring_buffer *ring)
676 struct pipe_control *pc = ring->private;
688 ret = intel_ring_begin(ring, 32);
692 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
695 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
696 intel_ring_emit(ring, ring->outstanding_lazy_request);
697 intel_ring_emit(ring, 0);
698 PIPE_CONTROL_FLUSH(ring, scratch_addr);
700 PIPE_CONTROL_FLUSH(ring, scratch_addr);
702 PIPE_CONTROL_FLUSH(ring, scratch_addr);
704 PIPE_CONTROL_FLUSH(ring, scratch_addr);
706 PIPE_CONTROL_FLUSH(ring, scratch_addr);
708 PIPE_CONTROL_FLUSH(ring, scratch_addr);
710 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
714 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
715 intel_ring_emit(ring, ring->outstanding_lazy_request);
716 intel_ring_emit(ring, 0);
717 intel_ring_advance(ring);
723 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
729 intel_ring_get_active_head(ring);
730 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
734 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
736 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
740 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
742 struct pipe_control *pc = ring->private;
747 gen5_ring_get_irq(struct intel_ring_buffer *ring)
749 struct drm_device *dev = ring->dev;
756 if (ring->irq_refcount++ == 0) {
757 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
767 gen5_ring_put_irq(struct intel_ring_buffer *ring)
769 struct drm_device *dev = ring->dev;
773 if (--ring->irq_refcount == 0) {
774 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
782 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
784 struct drm_device *dev = ring->dev;
791 if (ring->irq_refcount++ == 0) {
792 dev_priv->irq_mask &= ~ring->irq_enable_mask;
802 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
804 struct drm_device *dev = ring->dev;
808 if (--ring->irq_refcount == 0) {
809 dev_priv->irq_mask |= ring->irq_enable_mask;
817 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
819 struct drm_device *dev = ring->dev;
826 if (ring->irq_refcount++ == 0) {
827 dev_priv->irq_mask &= ~ring->irq_enable_mask;
837 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
839 struct drm_device *dev = ring->dev;
843 if (--ring->irq_refcount == 0) {
844 dev_priv->irq_mask |= ring->irq_enable_mask;
851 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
853 struct drm_device *dev = ring->dev;
854 drm_i915_private_t *dev_priv = ring->dev->dev_private;
857 /* The ring status page addresses are no longer next to the rest of
858 * the ring registers as of gen7.
861 switch (ring->id) {
872 } else if (IS_GEN6(ring->dev)) {
873 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
875 mmio = RING_HWS_PGA(ring->mmio_base);
878 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
883 bsd_ring_flush(struct intel_ring_buffer *ring,
889 ret = intel_ring_begin(ring, 2);
893 intel_ring_emit(ring, MI_FLUSH);
894 intel_ring_emit(ring, MI_NOOP);
895 intel_ring_advance(ring);
900 i9xx_add_request(struct intel_ring_buffer *ring)
904 ret = intel_ring_begin(ring, 4);
908 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
909 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
910 intel_ring_emit(ring, ring->outstanding_lazy_request);
911 intel_ring_emit(ring, MI_USER_INTERRUPT);
912 intel_ring_advance(ring);
918 gen6_ring_get_irq(struct intel_ring_buffer *ring)
920 struct drm_device *dev = ring->dev;
932 if (ring->irq_refcount++ == 0) {
933 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
934 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
937 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
938 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
948 gen6_ring_put_irq(struct intel_ring_buffer *ring)
950 struct drm_device *dev = ring->dev;
954 if (--ring->irq_refcount == 0) {
955 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
956 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
958 I915_WRITE_IMR(ring, ~0);
959 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
969 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
975 ret = intel_ring_begin(ring, 2);
979 intel_ring_emit(ring,
983 intel_ring_emit(ring, offset);
984 intel_ring_advance(ring);
992 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
999 ret = intel_ring_begin(ring, 4);
1003 intel_ring_emit(ring, MI_BATCH_BUFFER);
1004 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1005 intel_ring_emit(ring, offset + len - 8);
1006 intel_ring_emit(ring, MI_NOOP);
1007 intel_ring_advance(ring);
1009 struct drm_i915_gem_object *obj = ring->private;
1015 ret = intel_ring_begin(ring, 9+3);
1021 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1024 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1025 intel_ring_emit(ring, 0);
1026 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1027 intel_ring_emit(ring, cs_offset);
1028 intel_ring_emit(ring, 0);
1029 intel_ring_emit(ring, 4096);
1030 intel_ring_emit(ring, offset);
1031 intel_ring_emit(ring, MI_FLUSH);
1034 intel_ring_emit(ring, MI_BATCH_BUFFER);
1035 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1036 intel_ring_emit(ring, cs_offset + len - 8);
1037 intel_ring_advance(ring);
1044 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1050 ret = intel_ring_begin(ring, 2);
1054 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1055 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1056 intel_ring_advance(ring);
1061 static void cleanup_status_page(struct intel_ring_buffer *ring)
1065 obj = ring->status_page.obj;
1069 pmap_qremove((vm_offset_t)ring->status_page.page_addr, 1);
1070 kva_free((vm_offset_t)ring->status_page.page_addr,
1074 ring->status_page.obj = NULL;
1077 static int init_status_page(struct intel_ring_buffer *ring)
1079 struct drm_device *dev = ring->dev;
1097 ring->status_page.gfx_addr = obj->gtt_offset;
1098 ring->status_page.page_addr = (void *)kva_alloc(PAGE_SIZE);
1099 if (ring->status_page.page_addr == NULL) {
1103 pmap_qenter((vm_offset_t)ring->status_page.page_addr, &obj->pages[0],
1105 pmap_invalidate_cache_range((vm_offset_t)ring->status_page.page_addr,
1106 (vm_offset_t)ring->status_page.page_addr + PAGE_SIZE, FALSE);
1107 ring->status_page.obj = obj;
1108 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1110 intel_ring_setup_status_page(ring);
1112 ring->name, ring->status_page.gfx_addr);
1124 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1126 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1131 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE, BUS_SPACE_MAXADDR);
1137 if (INTEL_INFO(ring->dev)->gen >= 4)
1141 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1142 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1148 struct intel_ring_buffer *ring)
1154 ring->dev = dev;
1155 INIT_LIST_HEAD(&ring->active_list);
1156 INIT_LIST_HEAD(&ring->request_list);
1157 ring->size = 32 * PAGE_SIZE;
1158 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1161 init_waitqueue_head(&ring->irq_queue);
1165 ret = init_status_page(ring);
1169 BUG_ON(ring->id != RCS);
1170 ret = init_phys_hws_pga(ring);
1175 obj = i915_gem_alloc_object(dev, ring->size);
1182 ring->obj = obj;
1192 ring->virtual_start =
1194 dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, ring->size,
1196 if (ring->virtual_start == NULL) {
1202 ret = ring->init(ring);
1210 ring->effective_size = ring->size;
1211 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1212 ring->effective_size -= 128;
1217 pmap_unmapdev((vm_offset_t)ring->virtual_start, ring->size);
1222 ring->obj = NULL;
1224 cleanup_status_page(ring);
1228 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1233 if (ring->obj == NULL)
1236 /* Disable the ring buffer. The ring must be idle at this point */
1237 dev_priv = ring->dev->dev_private;
1238 ret = intel_ring_idle(ring);
1241 ring->name, ret);
1243 I915_WRITE_CTL(ring, 0);
1245 pmap_unmapdev((vm_offset_t)ring->virtual_start, ring->size);
1247 i915_gem_object_unpin(ring->obj);
1248 drm_gem_object_unreference(&ring->obj->base);
1249 ring->obj = NULL;
1251 if (ring->cleanup)
1252 ring->cleanup(ring);
1254 cleanup_status_page(ring);
1257 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1261 ret = i915_wait_seqno(ring, seqno);
1263 i915_gem_retire_requests_ring(ring);
1268 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1274 i915_gem_retire_requests_ring(ring);
1276 if (ring->last_retired_head != -1) {
1277 ring->head = ring->last_retired_head;
1278 ring->last_retired_head = -1;
1279 ring->space = ring_space(ring);
1280 if (ring->space >= n)
1284 list_for_each_entry(request, &ring->request_list, list) {
1290 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1292 space += ring->size;
1309 ret = intel_ring_wait_seqno(ring, seqno);
1313 if (WARN_ON(ring->last_retired_head == -1))
1316 ring->head = ring->last_retired_head;
1317 ring->last_retired_head = -1;
1318 ring->space = ring_space(ring);
1319 if (WARN_ON(ring->space < n))
1325 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1327 struct drm_device *dev = ring->dev;
1332 ret = intel_ring_wait_request(ring, n);
1336 CTR1(KTR_DRM, "ring_wait_begin %s", ring->name);
1345 ring->head = I915_READ_HEAD(ring);
1346 ring->space = ring_space(ring);
1347 if (ring->space >= n) {
1348 CTR1(KTR_DRM, "ring_wait_end %s", ring->name);
1362 CTR1(KTR_DRM, "ring_wait_end %s wedged", ring->name);
1366 CTR1(KTR_DRM, "ring_wait_end %s busy", ring->name);
1370 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1373 int rem = ring->size - ring->tail;
1375 if (ring->space < rem) {
1376 int ret = ring_wait_for_space(ring, rem);
1381 virt = (uint32_t *)((char *)ring->virtual_start + ring->tail);
1386 ring->tail = 0;
1387 ring->space = ring_space(ring);
1392 int intel_ring_idle(struct intel_ring_buffer *ring)
1397 /* We need to add any requests required to flush the objects and ring */
1398 if (ring->outstanding_lazy_request) {
1399 ret = i915_add_request(ring, NULL, NULL);
1405 if (list_empty(&ring->request_list))
1408 seqno = list_entry(ring->request_list.prev,
1412 return i915_wait_seqno(ring, seqno);
1416 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1418 if (ring->outstanding_lazy_request)
1421 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1424 int intel_ring_begin(struct intel_ring_buffer *ring,
1427 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1435 /* Preallocate the olr before touching the ring */
1436 ret = intel_ring_alloc_seqno(ring);
1440 if (unlikely(ring->tail + n > ring->effective_size)) {
1441 ret = intel_wrap_ring_buffer(ring);
1446 if (unlikely(ring->space < n)) {
1447 ret = ring_wait_for_space(ring, n);
1452 ring->space -= n;
1456 void intel_ring_advance(struct intel_ring_buffer *ring)
1458 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1460 ring->tail &= ring->size - 1;
1461 if (dev_priv->stop_rings & intel_ring_flag(ring))
1463 ring->write_tail(ring, ring->tail);
1467 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1470 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1474 /* Disable notification that the ring is IDLE. The GT
1483 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1487 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1489 /* Now that the ring is fully powered up, update the tail */
1490 I915_WRITE_TAIL(ring, value);
1491 POSTING_READ(RING_TAIL(ring->mmio_base));
1493 /* Let the ring send IDLE messages to the GT again,
1500 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1506 ret = intel_ring_begin(ring, 4);
1520 intel_ring_emit(ring, cmd);
1521 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1522 intel_ring_emit(ring, 0);
1523 intel_ring_emit(ring, MI_NOOP);
1524 intel_ring_advance(ring);
1529 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1535 ret = intel_ring_begin(ring, 2);
1539 intel_ring_emit(ring,
1543 intel_ring_emit(ring, offset);
1544 intel_ring_advance(ring);
1550 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1556 ret = intel_ring_begin(ring, 2);
1560 intel_ring_emit(ring,
1564 intel_ring_emit(ring, offset);
1565 intel_ring_advance(ring);
1572 static int blt_ring_flush(struct intel_ring_buffer *ring,
1578 ret = intel_ring_begin(ring, 4);
1592 intel_ring_emit(ring, cmd);
1593 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1594 intel_ring_emit(ring, 0);
1595 intel_ring_emit(ring, MI_NOOP);
1596 intel_ring_advance(ring);
1603 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1605 ring->name = "render ring";
1606 ring->id = RCS;
1607 ring->mmio_base = RENDER_RING_BASE;
1610 ring->add_request = gen6_add_request;
1611 ring->flush = gen7_render_ring_flush;
1613 ring->flush = gen6_render_ring_flush;
1614 ring->irq_get = gen6_ring_get_irq;
1615 ring->irq_put = gen6_ring_put_irq;
1616 ring->irq_enable_mask = GT_USER_INTERRUPT;
1617 ring->get_seqno = gen6_ring_get_seqno;
1618 ring->sync_to = gen6_ring_sync;
1619 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1620 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1621 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1622 ring->signal_mbox[0] = GEN6_VRSYNC;
1623 ring->signal_mbox[1] = GEN6_BRSYNC;
1625 ring->add_request = pc_render_add_request;
1626 ring->flush = gen4_render_ring_flush;
1627 ring->get_seqno = pc_render_get_seqno;
1628 ring->irq_get = gen5_ring_get_irq;
1629 ring->irq_put = gen5_ring_put_irq;
1630 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1632 ring->add_request = i9xx_add_request;
1634 ring->flush = gen2_render_ring_flush;
1636 ring->flush = gen4_render_ring_flush;
1637 ring->get_seqno = ring_get_seqno;
1639 ring->irq_get = i8xx_ring_get_irq;
1640 ring->irq_put = i8xx_ring_put_irq;
1642 ring->irq_get = i9xx_ring_get_irq;
1643 ring->irq_put = i9xx_ring_put_irq;
1645 ring->irq_enable_mask = I915_USER_INTERRUPT;
1647 ring->write_tail = ring_write_tail;
1649 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1651 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1653 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1655 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1657 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1658 ring->init = init_render_ring;
1659 ring->cleanup = render_ring_cleanup;
1679 ring->private = obj;
1682 return intel_init_ring_buffer(dev, ring);
1688 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1691 ring->name = "render ring";
1692 ring->id = RCS;
1693 ring->mmio_base = RENDER_RING_BASE;
1703 ring->add_request = i9xx_add_request;
1705 ring->flush = gen2_render_ring_flush;
1707 ring->flush = gen4_render_ring_flush;
1708 ring->get_seqno = ring_get_seqno;
1710 ring->irq_get = i8xx_ring_get_irq;
1711 ring->irq_put = i8xx_ring_put_irq;
1713 ring->irq_get = i9xx_ring_get_irq;
1714 ring->irq_put = i9xx_ring_put_irq;
1716 ring->irq_enable_mask = I915_USER_INTERRUPT;
1717 ring->write_tail = ring_write_tail;
1719 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1721 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1723 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1724 ring->init = init_render_ring;
1725 ring->cleanup = render_ring_cleanup;
1727 ring->dev = dev;
1728 INIT_LIST_HEAD(&ring->active_list);
1729 INIT_LIST_HEAD(&ring->request_list);
1731 ring->size = size;
1732 ring->effective_size = ring->size;
1733 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1734 ring->effective_size -= 128;
1736 ring->virtual_start = pmap_mapdev_attr(start, size,
1738 if (ring->virtual_start == NULL) {
1740 " ring buffer\n");
1745 ret = init_phys_hws_pga(ring);
1756 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1758 ring->name = "bsd ring";
1759 ring->id = VCS;
1761 ring->write_tail = ring_write_tail;
1763 ring->mmio_base = GEN6_BSD_RING_BASE;
1766 ring->write_tail = gen6_bsd_ring_write_tail;
1767 ring->flush = gen6_ring_flush;
1768 ring->add_request = gen6_add_request;
1769 ring->get_seqno = gen6_ring_get_seqno;
1770 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1771 ring->irq_get = gen6_ring_get_irq;
1772 ring->irq_put = gen6_ring_put_irq;
1773 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1774 ring->sync_to = gen6_ring_sync;
1775 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1776 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1777 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1778 ring->signal_mbox[0] = GEN6_RVSYNC;
1779 ring->signal_mbox[1] = GEN6_BVSYNC;
1781 ring->mmio_base = BSD_RING_BASE;
1782 ring->flush = bsd_ring_flush;
1783 ring->add_request = i9xx_add_request;
1784 ring->get_seqno = ring_get_seqno;
1786 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1787 ring->irq_get = gen5_ring_get_irq;
1788 ring->irq_put = gen5_ring_put_irq;
1790 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1791 ring->irq_get = i9xx_ring_get_irq;
1792 ring->irq_put = i9xx_ring_put_irq;
1794 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1796 ring->init = init_ring_common;
1798 return intel_init_ring_buffer(dev, ring);
1804 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1806 ring->name = "blitter ring";
1807 ring->id = BCS;
1809 ring->mmio_base = BLT_RING_BASE;
1810 ring->write_tail = ring_write_tail;
1811 ring->flush = blt_ring_flush;
1812 ring->add_request = gen6_add_request;
1813 ring->get_seqno = gen6_ring_get_seqno;
1814 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1815 ring->irq_get = gen6_ring_get_irq;
1816 ring->irq_put = gen6_ring_put_irq;
1817 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1818 ring->sync_to = gen6_ring_sync;
1819 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1820 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1821 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1822 ring->signal_mbox[0] = GEN6_RBSYNC;
1823 ring->signal_mbox[1] = GEN6_VBSYNC;
1824 ring->init = init_ring_common;
1826 return intel_init_ring_buffer(dev, ring);
1830 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1834 if (!ring->gpu_caches_dirty)
1837 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1841 ring->gpu_caches_dirty = false;
1846 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1852 if (ring->gpu_caches_dirty)
1855 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1859 ring->gpu_caches_dirty = false;