drm2/i915/intel_pm.c

692 	const struct cxsr_latency *latency;
699 		latency = &cxsr_latency_table[i];
700 		if (is_desktop == latency->is_desktop &&
701 		    is_ddr3 == latency->is_ddr3 &&
702 		    fsb == latency->fsb_freq && mem == latency->mem_freq)
703 			return latency;
731  * platforms but not overly aggressive on lower latency configs.
956  * @latency_ns: memory latency for the platform
979 	 * latency values.
981 	 * latency is usually a few thousand
1020 	const struct cxsr_latency *latency;
1024 	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1026 	if (!latency) {
1040 					pixel_size, latency->display_sr);
1050 					pixel_size, latency->cursor_sr);
1059 					pixel_size, latency->display_hpll_disable);
1068 					pixel_size, latency->cursor_hpll_disable);
1164 		DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1250  * Update drain latency registers of memory arbiter
1252  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1253  * to be programmed. Each plane has a drain latency multiplier and a drain
1254  * latency value.
1415 		/* self-refresh has much higher latency */
1534 		/* self-refresh has much higher latency */
1652 		DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1791 	 * WM3 is unsupported on ILK, probably because we don't have latency
1799 	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
1806 			    &sandybridge_display_wm_info, latency,
1807 			    &sandybridge_cursor_wm_info, latency,
1820 			    &sandybridge_display_wm_info, latency,
1821 			    &sandybridge_cursor_wm_info, latency,
1901 	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
1909 			    &sandybridge_display_wm_info, latency,
1910 			    &sandybridge_cursor_wm_info, latency,
1923 			    &sandybridge_display_wm_info, latency,
1924 			    &sandybridge_cursor_wm_info, latency,
1937 			    &sandybridge_display_wm_info, latency,
1938 			    &sandybridge_cursor_wm_info, latency,
1999 	/* WM3, note we have to correct the cursor latency */
2127 	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
2148 					    latency, &sprite_wm);
2213  *     lines), so need to account for TLB latency
2216  *     watermark = dotclock * bytes per pixel * latency
2217  *   where latency is platform & configuration dependent (we assume pessimal
2221  *     watermark = (trunc(latency/line time)+1) * surface width *
2226  *   and latency is assumed to be high, as above.
4162 				DRM_DEBUG_KMS("Failed to get proper latency. "
4172 				DRM_DEBUG_KMS("Failed to read display plane latency. "
4183 				DRM_DEBUG_KMS("Failed to read display plane latency. "
4194 				DRM_DEBUG_KMS("Failed to read display plane latency. "
4210 			DRM_INFO("failed to find known CxSR latency "