Lines Matching refs:m_n
756 struct intel_dp_m_n *m_n)
758 m_n->tu = 64;
759 m_n->gmch_m = (pixel_clock * bpp) >> 3;
760 m_n->gmch_n = link_clock * nlanes;
761 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
762 m_n->link_m = pixel_clock;
763 m_n->link_n = link_clock;
764 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
777 struct intel_dp_m_n m_n;
811 target_clock, adjusted_mode->clock, &m_n);
815 TU_SIZE(m_n.tu) | m_n.gmch_m);
816 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
817 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
818 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
820 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
821 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
822 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
823 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
825 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
826 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
827 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
828 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
831 TU_SIZE(m_n.tu) | m_n.gmch_m);
832 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
833 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
834 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);